Reduction In First Silicon Success


Every two years, Harry Foster, chief scientist for Mentor, a Siemens Business, works with Wilson Research to do a verification study. Those studies have influenced many in the industry, indicating where users are experiencing the most pain, spending their time, growing their team sizes and where money would be best spent. However, over the past four years, the ASIC industry has basically been i... » read more

Building AI SoCs


Ron Lowman, strategic marketing manager at Synopsys, looks at where AI is being used and how to develop chips when the algorithms are in a state of almost constant change. That includes what moves to the edge versus the data center, how algorithms are being compressed, and what techniques are being used to speed up these chips and reduce power. https://youtu.be/d32jtdFwpcE    ... » read more

From Physics To Applications


Jack Harding, president and CEO of eSilicon, sat down with Semiconductor Engineering to talk about the shift toward AI and advanced packaging, and the growing opportunities at 7nm at a time when Moore's Law has begun slowing down. What follows are excerpts of that conversation. SE: Over the past year, the industry has changed its focus from shrinking features and consolidation to all sorts o... » read more

Carmakers To Chipmakers: Where’s The Data?


The integration of electronics into increasingly autonomous vehicles isn't going nearly as smoothly as the marketing literature suggests. In fact, it could take years before some of these discrepancies are resolved. The push toward full autonomy certainly hasn't slowed down, but carmakers and the electronics industry are approaching that goal from very different vantage points. Carmakers and... » read more

eSilicon 7nm SerDes Hits 56Gbps


ASIC provider eSilicon focuses on high-performance devices for communications infrastructure, networking, and other data-center applications. Using 7nm TSMC pro- cess technology, it has developed ASIC-design platforms under the NeuASIC brand. Each platform includes hard and soft macros for networking applications along with a new architecture and intellectual-property (IP) library for building ... » read more

A Crisis In DoD’s Trusted Foundry Program?


The U.S. Department of Defense’s Trusted Foundry program is in flux due to GlobalFoundries’ recent decision to put 7nm on hold, raising national security concerns across the U.S. defense community. U.S. DoD and military/aerospace chip customers currently have access to U.S.-based “secure” foundry capacity down to 14nm, but that's where it ends. No other foundries provide similar “s... » read more

EUV’s Uncertain Future


The ground appears to be solidifying under EUV. Intel announced this week it is reducing its stake in ASML to less than 3%, the second such move in a year. Apparently ASML no longer needs outside help. According to the company's earnings report, ASML turned in net sales of €2.776 billion, a slight increase over the €2.447 billion (GAAP) the company reported in Q3 and way up over the €... » read more

Power Delivery Affecting Performance At 7nm


Complex interactions and dependencies at 7nm and beyond can create unexpected performance drops in chips that cannot always be caught by signoff tools. This isn't for lack of effort. The amount of time spent trying to determine if an advanced-node chip will work after it is fabricated has been rising steadily for several process nodes. Additional design rules handle everything from variation... » read more

Power Issues Grow For Cloud Chips


Performance levels in traditional or hyperscale data centers are being limited by power and heat caused by an increasing number of processors, memory, disk and operating systems within servers. The problem is so complex and intertwined, though, that solving it requires a series of steps that hopefully add up to a significant reduction across a system. But at 7nm and below, predicting exactly... » read more

ADAS Further Extends 7nm Challenges


As we discussed previously on the LPHP blog, 7nm nodes hold great promise for reducing power, improving performance and increasing density for next-generation chips, but also present a set of engineering challenges. When you factor in the standards set for autonomous vehicles (AV) and advanced driver assistance systems (ADAS) system-on-chips or SoCs, those challenges can more than double. Autom... » read more

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