tag: 7nm

Yield And Reliability Challenges At 7nm And Below
By PDF Solutions - 26 May, 2020 - Comments: 0

Layout Design Rules have been scaled very aggressively to enable the 7nm technology node without EUV. As a result, achieving acceptable performance and yield in High Volume Manufacturing (HVM) has become an extremely challenging task. Systematic yield and parametric variabilities have become quite significant. Moreover, due to overlay tolerance requirements and diminishing process windows, reli... » read more

Challenges In Stacking, Shrinking And Inspecting Next-Gen Chips
By Ed Sperling and Mark LaPedus - 21 May, 2020 - Comments: 0

Rick Gottscho, CTO of Lam Research, sat down with Semiconductor Engineering to discuss memory and equipment scaling, new market demands, and changes in manufacturing being driven by cost, new technologies, and the application of machine learning. What follows are excerpts of that conversation. SE: We have a lot of different memory technologies coming to market. What's the impact of that? ... » read more

‘More Than Moore’ Reality Check
By Ann Mutschler - 14 May, 2020 - Comments: 1

The semiconductor industry is embracing multi-die packages as feature scaling hits the limits of physics, but how to get there with the least amount of pain and at the lowest cost is a work in progress. Gaps remain in tooling and methodologies, interconnect standards are still being developed, and there are so many implementations of packaging that the number of choices is often overwhelming. ... » read more

New Uses For Manufacturing Data
By Ed Sperling - 12 May, 2020 - Comments: 0

The semiconductor industry is becoming more reliant on data analytics to ensure that a chip will work as expected over its projected lifetime, but that data is frequently inconsistent or incomplete, and some of the most useful data is being hoarded by companies for competitive reasons. The volume of data is rising at each new process node, where there are simply more things to keep track of,... » read more

Big Changes For eFPGAs
By Ed Sperling - 11 May, 2020 - Comments: 0

Geoff Tate, CEO of Flex Logix, talks with Semiconductor Engineering about the state of embedded FPGAs, why this is easier for some companies than others, why this is important for adding flexibility into an ASIC, and what are the main applications for this technology. » read more

Reliability Monitoring Of GUC 7nm High-Bandwidth Memory (HBM) Subsystem
By proteanTecs - 27 Apr, 2020 - Comments: 0

This white paper presents the use of proteanTecs’ Proteus for HBM subsystem reliability based on deep data analytics and enhanced visibility, overcoming the limitations of advanced heterogeneous packaging. It will describe the operation concept and provide results from a GUC 7nm HBM Controller ASIC. A typical CoWoS chip has hundreds of thousands of micro-bumps (u-bumps). 3-8 u-bumps are us... » read more

Identifying And Preventing Process Failures At 7nm
By Qingpeng Wang - 20 Apr, 2020 - Comments: 0

Device yield is highly dependent upon proper process targeting and variation control of fabrication steps, particularly at advanced nodes with smaller feature sizes. Traditionally, cross-correlation and analysis of thousands of test data points have been required to identify and prevent process failures. This is very costly in terms of both time and money. Fortunately, semiconductor virtual fab... » read more

Week In Review: Manufacturing, Test
By Mark LaPedus - 17 Apr, 2020 - Comments: 0

Chipmakers TSMC posted mixed results for the quarter, although there was a capital spending surprise. “It maintained its 2020 capex at $15B-$16B despite smartphone softness, primarily to support a strong 5nm ramp, led by demand from 5G and HPC customers,” said Weston Twigg, an analyst at KeyBanc, in a research note. “Despite lowering its industry outlook, TSMC still expects to grow its o... » read more

Designing Ultra Low Power AI Processors
By Ann Mutschler - 09 Apr, 2020 - Comments: 0

AI chip design is beginning to shift direction as more computing moves to the edge, adding a level of sophistication and functionality that typically was relegated to the cloud, but in a power envelope compatible with a battery. These changes leverage many existing tools, techniques and best practices for chip design. But they also are beginning to incorporate a variety of new approaches tha... » read more

Improving EUV Process Efficiency
By Mark LaPedus - 19 Mar, 2020 - Comments: 2

The semiconductor industry is rethinking the manufacturing flow for extreme ultraviolet (EUV) lithography in an effort to improve the overall process and reduce waste in the fab. Vendors currently are developing new and potentially breakthrough fab materials and equipment. Those technologies are still in R&D and have yet to be proven. But if they work as planned, they could boost the flo... » read more

← Older posts Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2024 SMG   |  Terms of Service  |  Privacy Policy