tag: 7nm

Mask Making Issues With EUV
By Mark LaPedus - 17 Oct, 2019 - Comments: 0

Semiconductor Engineering sat down to discuss lithography and photomask trends with Bryan Kasprowicz, director of technology and strategy and a distinguished member of the technical staff at Photronics; Thomas Scheruebl, director of strategic business development and product strategy at Zeiss; Noriaki Nakayamada, senior technologist at NuFlare; and Aki Fujimura, chief executive of D2S. What fol... » read more

Stacking Memory On Logic, Take Two
By Ed Sperling - 19 Sep, 2019 - Comments: 1

True 3D-ICs, where a memory die is stacked on top of a logic die using through-silicon vias, appear to be gaining momentum. There are a couple reasons why this is happening, and a handful of issues that need to be considered before even seriously considering this option. None of this is easy. On a scale of 1 to 10, this ranks somewhere around 9.99, in part because the EDA tools needed to rem... » read more

Trading Off Power And Performance Earlier In Designs
By Ann Mutschler - 12 Sep, 2019 - Comments: 0

Optimizing performance, power and reliability in consumer electronics is an engineering feat that involves a series of tradeoffs based on gathering as much data about the use cases in which a design will operate. Approaches vary widely by market, by domain expertise, and by the established methodologies and perspective of the design teams. As a result, one team may opt for a leading-edge des... » read more

Test On New Technology’s Frontiers
By SE Staff - 10 Sep, 2019 - Comments: 2

Semiconductor testing is getting more complicated, more time-consuming, and increasingly it requires new approaches that have not been fully proven because the technologies they are addressing are so new. Several significant shifts are underway that make achieving full test coverage much more difficult and confidence in the outcome less certain. Among them: Devices are more connected an... » read more

Nvidia’s Top Technologists Discuss The Future Of GPUs
By SE Staff - 10 Sep, 2019 - Comments: 0

Semiconductor Engineering sat down to discuss the role of the GPU in artificial intelligence, autonomous and assisted driving, advanced packaging and heterogeneous architectures with Bill Dally, Nvidia’s chief scientist, and Jonah Alben, senior vice president of Nvidia’s GPU engineering, at IEEE’s Hot Chips 2019 conference. What follows are excerpts of that conversation. SE: There are ... » read more

IP’s Growing Impact On Yield And Reliability
By Ann Mutschler - 04 Sep, 2019 - Comments: 0

Chipmakers are finding it increasingly difficult to achieve first-pass silicon with design IP sourced internally and from different IP providers, and especially with configurable IP. Utilizing poorly qualified IP and waiting for issues to appear during the design-to-verification phase just before tape-out can pose high risks for design houses and foundries alike in terms of cost and time to... » read more

Signoff-Compatible CDC
By Ed Sperling - 29 Jul, 2019 - Comments: 2

Tanveer Singh, senior staff consulting applications engineer at Synopsys, explains why netlist clock domain crossing is now an essential complement to RTL CDC, why CDC issues are worse at advanced nodes and in AI chips, and why dealing with CDC effectively is becoming a competitive requirement for performance and low power. » read more

Node Within A Node
By Ed Sperling - 24 Jul, 2019 - Comments: 0

Enough margin exists in manufacturing processes to carve out the equivalent of a full node of scaling, but shrinking that margin will require a collective push across the entire semiconductor manufacturing supply chain. Margin is built into manufacturing at various stages to ensure that chips are manufacturable and yield sufficiently. It can include everything from variation in how lines are... » read more

Test Chips Play Larger Role At Advanced Nodes
By Ann Mutschler - 27 Jun, 2019 - Comments: 0

Test chips are becoming more widespread and more complex at advanced process nodes as design teams utilize early silicon to diagnose problems prior to production. But this approach also is spurring questions about whether this approach is viable at 7nm and 5nm, due to the rising cost of prototyping advanced technology, such as mask tooling and wafer costs. Semiconductor designers have long b... » read more

CEO Outlook: Rising Costs, Chiplets, And A Trade War
By Ed Sperling - 26 Jun, 2019 - Comments: 0

Semiconductor Engineering sat down to discuss what's changing across the semiconductor industry with Wally Rhines, CEO emeritus at Mentor, a Siemens Business; Jack Harding, president and CEO of eSilicon; John Kibarian, president and CEO of PDF Solutions; and John Chong, vice president of product and business development for Kionix. What follows are excerpts of that discussion, which was held in... » read more

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