Test On New Technology’s Frontiers

Where the gaps are and what that means for coverage and reliability.


Semiconductor testing is getting more complicated, more time-consuming, and increasingly it requires new approaches that have not been fully proven because the technologies they are addressing are so new.

Several significant shifts are underway that make achieving full test coverage much more difficult and confidence in the outcome less certain. Among them:

  • Devices are more connected and dependent on other devices, whether that is the cloud, the edge, or a car with V2X connectivity. That makes performance and reliability dependent on a system of systems, which often involve multiple vendors and technologies that are not fully developed.
  • There is a big push toward customization and optimization for many devices, particularly where AI and machine learning are part of the solution. How those devices behave and change over time isn’t clear because this technology is so new, and how to ensure that it is reliable is equally unclear.
  • New architectures are pushing transistors and memories much more closely together, adding more heterogeneous processing elements and memories, and creating high-speed interconnects to move data around on-chip and off-chip. Many of these architectures are in a constant state of flux, defined in part by changing algorithms and in part by changing end market demands.

With 5G systems and flexible circuits, the technology is so new that proven test strategies don’t exist. In automotive and other safety-critical markets, devices are expected to last for a couple decades, but how to consistently achieve that isn’t clear—in part because these devices will need to be updated throughout their lifetimes. And at the most advanced nodes and in some advanced packaging, finding defects is becoming much more difficult without the addition of analytics and regression types of testing.

Without passing test, no technology advances. But at this point it’s not always clear what exactly needs to be tested or how that testing should be done. Semiconductor Engineering examined a number of these new technologies and approaches, talking with dozens of experts about what’s changing, how test needs to adapt, and where gaps still exist.

Automotive safety-critical tests have standards to follow, specifically ISO 26262 and various ASIL levels. “Depending on the ASIL Level A, B, C or D, you need to achieve certain metric levels,” said Steve Pateras, senior director of marketing for the Test Products Design Group at Synopsys. “And depending on that ASIL level, those metrics have to be a certain value—90%, 95%, 99%. But how do you measure those metrics accurately? And once those metrics are measured, how do you improve them if necessary? Up until now it’s been very much an ad hoc methodology. That includes spreadsheets, some ad hoc tools and, more recently, people have been using fault injection-based approaches—simulation approaches where they’ll inject a fault and they’ll look to see if the circuit will tolerate the fault. And that will help us drive measurements of these various metrics.”

Those approaches are time consuming, though, and that translates into a much higher cost for test and slows down the whole manufacturing process. And the problems get even worse once 10/7nm logic is thrown into the mix. That kind of density is necessary for the AI systems in autonomous vehicles, but testing chips developed at these nodes for automotive applications has never been done before. In fact, no advanced-node chip ever has been used outside of a controlled environment, whether that is a smart phone or a data center. And smart phones will not turn on when the temperature gets too hot, which is not an option for a chip in a safety-critical system.

“The construction of 7nm technology is such that you can’t see that easily using conventional approaches,” said Dennis Ciplickas, vice president of characterization solutions at PDF Solutions. “Conventional in-line inspection, even e-beam, conventional product test, the variability involved and the types of failures you can have, have reached a point where the chips are big and complex enough, and the applications of those chips are critical enough, that people are open to how to get more data. How do you get under the hood of this thing and not get burned later? The automotive piece is interesting because that market used to be super conservative and low-tech. 7nm in automotive is new. AI is now safety-critical.”

That creates all sorts of issues for test, though. “The biggest problem with advanced nodes is that you need to get reliable data for the stress screening test, and you don’t have that before an advanced node has been in production for a while,” said Gert Jørgensen, vice president of sales and marketing at DELTA Microelectronics.

Even where reliable data is available, there is a reluctance to share it in the automotive market for competitive reasons. “The Tier 1s and the OEMs are competing,” said Doug Farrell, principal solutions manager for transportation at National Instruments. “So you have Tier 1s building an autonomous stack, and OEMs are investing in autonomy and AI. As a result, no one is sharing data. At the same time, they’re both investing millions of dollars in startups, but those startups may get bought by their competitors, so they’re even reluctant to share data with the companies they’ve invested in.”

That doesn’t help advance knowledge for testing of these systems. On top of that, there are random failures for which there is no known cause or solution.

“You can’t test for the random failures,” said Jørgensen. “You go through this screening test of devices and expose them, and if they pass a lot of acceptance tests, which take 128 hours—that’s a week—and you’ve said that they pass, you’ve judged them as good devices. And if the failure happens out in the field, of course, we do a failure analysis. I know the car manufacturers are registering all failures to see if each failure is a periodic failure or a random failure. They have fast reporting systems, so that when we have found the failure, they will detect if it has influence on the rest of the population. If they say this is a random failure, they will store it and see if there’s more coming. If it’s a failure that can be fixed, they do something about it. There are quality measurements on how to deal with random failures and procedures. They know exactly if this device when it fails out there, when it was produced, how it was produced, which person was involved.”

5G testing
5G seems to infiltrate any discussion about testing these days, in part because the market is expected to balloon and in part because there are so many unknowns, particularly in the millimeter wave spectrum. Those gaps need to be filled in without sacrificing the ability to process billions of devices each year.

“The current frequencies clearly aren’t going away, so we have to continue to test those in this way that we have done in the past,” said Neill Mullinger, product manager in the vertical market solutions group at Mentor, a Siemens Business. “But then you augment that with new solutions to deal with the expanded frequencies of 5G. That is an area where the extant family of testers allows you to do a lot of that. Adding virtualization allows us to set up a test environment for the lab or the field and run the exact same environment. It’s an area that’s going to evolve over time.”

He noted this was one of the drivers behind Mentor’s acquisition of Sarokal Test Systems last year. Sarokal makes 5G front-haul test equipment.

“They do testers for the field and in the lab, and we can now bring that forward and virtualize what they have so it can be used pre-silicon,” Mullinger said. “As you are respinning things, you are able to do a lot of the analysis that you do in the lab much sooner in the process and try out all different kinds of scenarios.”

The emphasis here is on experimentation, because much of this has never been done before.

“5G is a complicated system of systems,” said Ian Dennison, senior group director for customized IC and PCB group at Cadence. “It involves a lot of new moving parts. We’ve got the optical front haul to the small radio heads, and there are many of them. We’ve got this concentrated radio access network baseband edge compute going on, and this whole system of systems needs testing. It will need some sort of over-the-air test. We can do the emulation and FPGA prototyping and simulation, of course, but in addition it is going to be a lot of real-world testing. Part of this is an expectation-management problem. We should expect that our 5G systems start to improve over time as the AI systems start to kick in and start to develop better quality of service. But straight out the box, it may not be perfect. So testing as it were is going to be a continuous thing, and something the network operators are going to be relying on to improve the quality of their service.”

This is especially evident with 5G antenna arrays, because there are no exposed leads to connect to a tester.

“It starts from the mathematical from the tools that are doing the antenna design,” said Peter Zhang, R&D manager in Synopsys’ solutions group. “But people do have to prototype and figure out a way to be able to test it in a more realistic environment so they can see the calculated gain they are accomplishing with the antenna. This is actually the same thing applied to the digital design part of the ASIC, because we can all have very nice simulated results with the formulas. We can have a very nice model describing what is the radio environment around us, and there are so many models available. But when you go to 5G and you run data in the millimeter wave, which is a lot more complex than what we’ve had so far, do the models really represent what we’re going to deal with when our system is outside?”

The answer so far isn’t clear.

“If engineers are used to working at lower frequencies on these earlier cellular applications, and then they transition to working on 5G at higher frequencies, all of sudden all the rules are more stringent, all the rules of thumb go out the door, and you have to do a more thorough design,” said Mike Leffel, an application engineer at Rohde & Schwarz.

Flexible circuits
Flexible electronics add a brand new challenge for testing. Printed circuits are just beginning to gain traction in the market, and testing needs to catch up as these devices are used across a variety of markets where conditions may be extreme and where sensors have never been used before, such as on a valve or piece of machinery.

Source: Brewer Science.

“We try to borrow as much as we can from the traditional rigid printed circuit board community,” said Will Stone, director of printed electronics integrations and operations at Brewer Science. “We’re looking environmental stresses and other issues. The challenges are twofold. Number one, there are traditional components being mounted to a flexible circuit board. We need to make sure the joints, whether those are conductive epoxy or some other material, can withstand the motion, because they’re not designed for that. Second, we have to look at the connecting traces themselves. Just by flexing you can get micro-cracking. We run those through the usual gamut of testing, such as environmental chambers, stressing the flexing thousands to millions of cycles, just to ensure the integrity of the device.”

On rigid chips, there are latent defects that may not show up for years. Conductive inks and solder add a whole new dimension to what needs to be tested.

“The inks are pretty stable once you get the process down. It’s the epoxies and solders that we use. A lot of these weren’t designed to flex at all — especially the solders. We’re playing in a rigid world and trying to make a rigid world flexible. That’s the challenge. Any joint is where you will have the greatest area of concern.”

So far, there is too little history to show how well this kind of technology will fare over time under extreme conditions involving heat, cold and vibration. So while companies like Brewer are accelerating testing, both physically and through simulation, it still takes time to gather enough data about what can go wrong and how to fix it. But one thing is clear—if a defect is detected, it’s easier to replace the board than to fix it.

“It’s heading toward a disposable type of approach, because re-work is extremely difficult on these circuits,” he added. “We have had some success at doing rework, but it’s time consuming and painstaking. It’s usually more economical to replace it with a new board, even in the R&D phases.”

Advanced packaging, heterogenous architectures
Finally, advanced packaging adds all sorts of new challenges to test, as well as inspection, and those challenges grow exponentially as chips are more tightly integrated into dense packages or when they use unusual shapes, such as increasingly skinny pillars on a fan-out.

“The need is clearly there to inspect these packages for a reasonable cost,” said Subodh Kulkarni, CEO of CyberOptics. “But there also are a lot of new structures like bumps and pillars, and the pillars are getting skinny and tall. That is creating a challenge.”

Alongside of that, designs increasingly are heterogeneous and at least semi-customized for a particular use case or application. And in the case of AI chips, they adapt throughout their lifetime based upon probabilities. How to test for reliability and even characterize field failures is a major challenge.

Many vendors working at the most advanced nodes also utilize advanced packaging of some sort because while scaling provides density, it doesn’t provide significant improvements in power and performance. Architectural changes are needed for that, and this becomes particularly important in AI applications and in chips developed for 5G millimeter wave infrastructure.

“We’re working with ATE vendors on this,” said Calvin Cheung, vice president of packaging at ASE. “To develop this at a compelling cost point, it has to use the existing silicon infrastructure. That means wafer-level, package-level testing. We’re working with ATE vendors to figure out a test solution. We have to solve all of the over-the-air test issues and the EMI test issues, and it has to be done at a reasonable cost. That’s the issue that we’re wrestling with now.”

Taken as a whole, these are some of the most interesting challenges the test world has ever witnessed. In the past, test was largely a separate step in a multi-step manufacturing process. It is now a key consideration for every step of the design through manufacturing flow, and it will require much tighter integration into these new technologies and markets as they are developed.

Or looked at another way, test is now a critical part of the development of new technologies and markets, and it could well become a gating factor if it cannot keep up.

Related Stories
Using Better Data To Shorten Test Time
More sensors plus machine learning are making it possible to focus testing where it has the most impact.
Solving 5G’s Thorniest Issues
Incomplete roadmaps and continued uncertainty about millimeter-wave technology make this technology’s future hazy, but solutions are in the works.
Gaps Emerge In Automotive Test
Reliability requires different parts to work in sync, and much more time-consuming testing and simulation.
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Peter Manoj says:

Very good article Ed and team.


Interesting article!

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