Chiplets Enter The Supercomputer Race


Several entities from various nations are racing each other to deliver and deploy chiplet-based exascale supercomputers, a new class of systems that are 1,000x faster than today’s supercomputers. The latest exascale supercomputer CPU and GPU designs mix and match complex dies in advanced packages, adding a new level of flexibility and customization for supercomputers. For years, various na... » read more

Blog Review: March 16


Ansys' Peter Hallschmid and Sandra Gely look at why, compared to rain and fog, snow is a different challenging environment for automotive sensors and how the random pattern of snowfall, properties of each flake, and the various distance between flakes play havoc on detecting objects. Siemens' Chuck Battikha focuses on how to protect against random hardware faults, the added costs of includin... » read more

Seven Hardware Advances We Need to Enable The AI Revolution


The potential, positive impact AI will have on society at large is impossible to overestimate. Pervasive AI, however, remains a challenge. Training algorithms can take inordinate amounts of power, time, and computing capacity. Inference will also become more taxing with applications such as medical imaging and robotics. Applied Materials estimates that AI could consume up to 25% of global elect... » read more

Power Now First-Order Concern In More Markets


Concerns about energy and power efficiency are becoming as important as performance in markets where traditionally there has been a significant gap, setting the stage for significant shifts in both chip architectures and in how those ICs are designed in the first place. This shift can be seen in a growing number of applications and vertical segments. It includes mobile devices, where batteri... » read more

Why Comparing Processors Is So Difficult


Every new processor claims to be the fastest, the cheapest, or the most power frugal, but how those claims are measured and the supporting information can range from very useful to irrelevant. The chip industry is struggling far more than in the past to provide informative metrics. Twenty years ago, it was relatively easy to measure processor performance. It was a combination of the rate at ... » read more

Robots Become More Useful In Factories


Most people associate factory automation with large robotic machines, such as those that weld automobile chassis on assembly lines. But as prices drop and technology improves, robots are being deployed for smaller and more varied tasks, and they are getting better at all of them. Inside of factories, robots can significantly improve output, consistency, and reliability. They can work around ... » read more

Blog Review: March 9


Arm's Ajay Joshi investigates how to select the right benchmark for CPUs used in the Home device market, such as digital television and set-top box/over-the-top devices. Ansys' Jon Kordell checks out how reliability physics simulations and physical component characterization can support component swapping in high-reliability applications when the original part is unavailable due to supply ch... » read more

Week In Review: Manufacturing, Test


Packaging ASE, AMD, Arm, Google, Intel, Meta, Microsoft, Qualcomm, Samsung, and TSMC have announced the formation of a consortium that will establish a die-to-die interconnect standard and foster an open chiplet ecosystem. The founding companies also ratified the UCIe specification, an open industry standard developed to establish a standard interconnect at the package level. The UCIe 1.0 s... » read more

Week In Review: Design, Low Power


Tools & IP Imperas Software introduced the RISC-V Verification Interface (RVVI). The open standard and methodology can be adapted to any configuration permitted within the RISC-V specifications. RVVI defines interfaces between RTL, reference model, and testbench for RISC-V design verification, with the aim of making RISC-V processor DV reusable. It supports multi-hart, superscalar, and out... » read more

Blog Review: March 2


Arm's Charlotte Christopherson checks out SpiNNaker1, a project to develop a massively parallel, manycore supercomputer architecture that mimicked the interactions of biological neurons, and its follow up, SpiNNaker2, a hybrid system that combines statistical AI and neuromorphic computing. Cadence's Paul McLellan looks at open and generic PDKs that can be used by researchers and in education... » read more

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