tag: BEOL

Detailed RF Characterization of Ultra-Thin Indium Oxide Transistors
By Technical Paper Link - 13 Sep, 2022 - Comments: 0

A new technical paper titled "Record RF Performance of Ultra-thin Indium Oxide Transistors with Buried-gate Structure" was published by researchers at Purdue University and won the 2022 Device Research Conference Best Student Paper Award (DRC 2022 held in June). According to this Purdue University news release, "In this work, the radio frequency (RF) performance of indium oxide transistors w... » read more

New Materials Open Door To New Devices
By Katherine Derbyshire - 21 Jul, 2022 - Comments: 0

Integrating 2D materials into conventional semiconductor manufacturing processes may be one of the more radical changes in the chip industry’s history. While there is pain and suffering associated with the introduction of any new materials in semiconductor manufacturing, transition metal dichalcogenides (TMDs) support a variety of new device concepts, including BEOL transistors and single-... » read more

New Method For BEOL Overlay And Process Margin Characterization
By PDF Solutions - 07 Jun, 2022 - Comments: 0

This paper presents a new method, design for inspection (DFI) to characterize overlay. Using design-assisted voltage contrast measurement, the method enables in-line test and monitoring of process induced OVL and CD variation of backend-of line (BEOL) features with litho-etch-lithoetch (LELE) patterning. While only some of the features of multi-color patterning scheme are chosen to be aligned d... » read more

There Is Plenty Of Room At The Top: Imagining Miniaturized Electro-Mechanical Switches In Low-Power Computing Applications
By Gerold Schröpfer - 19 May, 2022 - Comments: 0

The first computers were built using electro-mechanical components, unlike today’s modern electronic systems. Alan Turing’s cryptanalysis multiplier and Konrad Zuse’s Z2 were invented and built in the first half of the 20th century, and were among the first computers ever constructed. Electro-mechanical switches and relays performed logic operations in these machines. Even after computers... » read more

BEOL Integration For The 1.5nm Node And Beyond
By Assawer Soussou - 25 Apr, 2022 - Comments: 0

As we approach the 1.5nm node and beyond, new BEOL device integration challenges will be presented. These challenges include the need for smaller metal pitches, along with support for new process flows. Process modifications to improve RC performance, reduce edge placement error, and enable challenging manufacturing processes will all be required. To address these challenges, we investigated th... » read more

Hiding Security Keys Using ReRAM PUFs
By Katherine Derbyshire - 21 Apr, 2022 - Comments: 2

Resistive RAM and physically unclonable functions (PUFs) have been gaining traction for completely different reasons, but when combined they create an extremely secure and inexpensive way of storing authentication keys. As security concerns shift from purely software to a combination of hardware and software, chipmakers and systems companies have been scrambling to figure out how to prevent ... » read more

2D Semiconductors Make Progress, But Slowly
By Katherine Derbyshire - 28 Feb, 2022 - Comments: 2

Researchers are looking at a variety of new materials at future nodes, but progress remains slow. In recent years, 2D semiconductors have emerged as a leading potential solution to the problem of channel control in highly scaled transistors. As devices shrink, the channel thickness should shrink proportionally. Otherwise, the gate capacitance won’t be large enough to control the flow of cu... » read more

The Effect Of Pattern Loading On BEOL Yield And Reliability During Chemical Mechanical Planarization
By Taeyon (TY) Oh - 20 Jan, 2022 - Comments: 0

Chemical mechanical planarization (CMP) is required during semiconductor processing of many memory and logic devices. CMP is used to create planar surfaces and achieve uniform layer thickness during semiconductor manufacturing, and to optimize the device topology prior to the next processing step. Unfortunately, the surface of a semiconductor device is not uniform after CMP, due to different re... » read more

Will Monolithic 3D DRAM Happen?
By Bryon Moyer - 09 Sep, 2021 - Comments: 1

As DRAM scaling slows, the industry will need to look for other ways to keep pushing for more and cheaper bits of memory. The most common way of escaping the limits of planar scaling is to add the third dimension to the architecture. There are two ways to accomplish that. One is in a package, which is already happening. The second is to sale the die into the Z axis, which which has been a to... » read more

Advancing To The 3nm Node And Beyond: Technology, Challenges And Solutions
By Michael Hargrove - 19 Aug, 2021 - Comments: 0

It seems like yesterday that finFETs were the answer to device scaling limitations imposed by shrinking gate lengths and required electrostatics. The introduction of finFETs began at the 22nm node and has continued through the 7nm node. Beyond 7nm, it looks like nanosheet device structures will be used for at least the 5nm and probably the 3nm nodes. The nanosheet device structure is the brainc... » read more

← Older posts Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2024 SMG   |  Terms of Service  |  Privacy Policy