tag: Breker Verification Systems

Get Ready For Verification 3.0
By Brian Bailey - 24 May, 2018 - Comments: 0

Jim Hogan, managing partner of Vista Ventures, LLC, is perhaps the best-known investor in the EDA space. Recently, he has been focusing time and attention on verification startups, including cloud technology company Metrics, and Portable Stimulus pioneer Breker Verification Systems. This adds to his longer-term commitment to formal verification with OneSpin Solutions. These companies are part ... » read more

The Week In Review: Design
By Jesse Allen - 06 Apr, 2018 - Comments: 0

Tools Mentor, a Siemens business, filled in the last of the hardware configurations for its Veloce Strato emulation family, creating a full upgrade path. Users can initially purchase only the hardware that they need (StratoTiL) and if later they require more capacity (StratoTi) or the ability to handle larger designs (StratoT), they can incrementally add the necessary hardware to their existin... » read more

The Week In Review: Design
By Jesse Allen - 09 Feb, 2018 - Comments: 0

M&A Synopsys acquired PhoeniX Software, expanding its photonic integrated circuit design range. Founded in 2003 and based in the Netherlands, PheoniX adds photonic aware physical layout capabilities, enabled by support for foundry-specific PDKs, along with a full photonic chip design package. Terms of the deal were not disclosed. Siemens PLM Software will acquire Sarokal Test Systems, w... » read more

The Week In Review: Design
By Jesse Allen - 16 Jun, 2017 - Comments: 0

M&A Verific acquired Invionics' entire INVIO technology portfolio, adding a high-level scripting interface with 100 high-level APIs to its Parser Platform of approximately 2,000 low-level SystemVerilog and VHDL APIs. An R&D group from the company will also join Verific. Portable Stimulus An Early Adopter release of the Portable Stimulus specification has been made publicly availabl... » read more

Custom Chip Verification Issues Grow
By Ann Mutschler - 29 Mar, 2017 - Comments: 0

With the transition to finFETs, design conditions have grown more intense. They now include a wider PVT range and less headroom. As a result, electronic systems for applications such as mobile, consumer, and automotive increasingly are becoming more difficult to design due to the exacting performance requirements of these applications. This is particularly evident in custom design, including... » read more

The Week In Review: Design/IoT
By Ed Sperling - 11 Sep, 2015 - Comments: 0

Tools Mentor Graphics rolled out a new version of its tool for transferring PCB designs into data for fabrication, assembly and test. The company also announced that its debug environment will support the UPF Low Power Successive Refinement Methodology. Deals Ansys and Cray are claiming the world's record for simulation by scaling 129,000 cores. That's about 4X the previous record.  Ansys... » read more

Software-Driven Verification (Part 3)
By Brian Bailey - 10 Feb, 2015 - Comments: 0

[getkc id="10" comment="Functional Verification"] has been powered by tools that require hardware to look like the kinds of systems that were being designed two decades ago. Those limitations are putting chips at risk and a new approach to the problem is long overdue. Semiconductor Engineering sat down with Frank Schirrmeister, group director, product marketing for System Development Suite at [... » read more

Tools And Flows In 2015
By Brian Bailey - 29 Jan, 2015 - Comments: 0

This year more than 26 people provided predictions for 2015. Most of these came from the EDA industry, so the results may be rather biased. However, ecosystems are coming closer together in many parts of the semiconductor food chain, meaning that the EDA companies often can see what is happening in dependent industries and in the system design houses. Thus their predictions may have already res... » read more

Software-Driven Verification (Part 1)
By Brian Bailey - 18 Dec, 2014 - Comments: 1

[getkc id="10" comment="Functional Verification"] has been powered by tools that require hardware to look like the kinds of systems that were being designed two decades ago. Those limitations are putting chips at risk and a new approach to the problem is long overdue. Semiconductor Engineering sat down with Frank Schirrmeister, group director, product marketing for System Development Suite at [... » read more

Problems Lurk In SoC Boundaries
By Brian Bailey - 04 Dec, 2014 - Comments: 0

Interfaces always have been a problem, because only rarely does anyone have responsibility for them. Responsibilities generally are tied to functional blocks with the prevailing notion that if all blocks do the right thing, they will also behave correctly when brought together. Design teams that believe this eventually find out the fallacy of this assumption. To make matters worse, these are of... » read more

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