tag: Cadence

Blog Review: Jan. 4
By Jesse Allen - 04 Jan, 2023 - Comments: 0

Siemens EDA's Harry Foster investigates the percentage of total IC/ASIC project time spent in verification and increasing engineering headcount, particularly growing demand for verification engineers. Synopsys' Stelios Diamantidis argues that retargeting older chips using AI offers a way to move chip designs between nodes and absorb the market’s excess capacity. Cadence's Paul McLellan ... » read more

Tensilica DSPs Support In Eigen Library
By Cadence - 04 Jan, 2023 - Comments: 0

Eigen is a high-level C++ library of template headers for linear algebra, matrix and vector operations, geometrical transformations, numerical solvers, and related algorithms. Eigen is open-source software licensed under the Mozilla Public License 2.0 (MPL2). Eigen is implemented using the expression templates metaprogramming technique, meaning it builds expression trees at compile time... » read more

Designing For Multiple Die
By Ann Mutschler - 21 Dec, 2022 - Comments: 1

Integrating multiple die or chiplets into a package is proving to be very different than putting them on the same die, where everything is developed at the same node using the same foundry process. As designs become more heterogeneous and disaggregated, they need to be modeled, properly floor-planned, verified, and debugged in the context of a system, rather than as individual components. Typi... » read more

IEDM Keynote: Ann Kelleher On Future Technology
By Paul McLellan - 21 Dec, 2022 - Comments: 0

IEDM 2022 celebrated 75 Years of the Transistor. I can't imagine anything else invented in the last 75 years has had as much effect on my life, and probably yours, too. After the awards session, the conference got underway with a keynote by Ann Kelleher, Executive Vice President and General Manager of Technology Development at Intel. It was titled "Celebrating 75 Years of the Transistor! A L... » read more

Accelerate The Algorithm To Silicon Development With Stratus HLS
By Cadence - 21 Dec, 2022 - Comments: 0

Growth in demand for artificial intelligence (AI) and digital signal processing (DSP) applications, coupled with advances in semiconductor process technology, drives increasingly denser SoCs. These complex SoCs further challenge the design team’s ability to meet performance, power, and area (PPA) goals within tight time-to-market windows. We need automated and targeted solutions that efficien... » read more

Blog Review: Dec. 20
By Jesse Allen - 20 Dec, 2022 - Comments: 0

Synopsys' Twan Korthorst explains how PDKs can help accelerate the photonic IC design process by offering building blocks such as several types of waveguides, passive devices like splitters, combiners, and filters, along with active devices such as phase shifters, detectors, semiconductor optical amplifiers, and lasers. Siemens EDA's Harry Foster examines IC and ASIC design trends, including... » read more

The March Toward Chiplets
By Ed Sperling and Karen Heyman - 15 Dec, 2022 - Comments: 0

The days of monolithic chips developed at the most advanced process nodes are rapidly dwindling. Nearly everyone working at the leading edge of design is looking toward some type of advanced packaging using discrete heterogeneous components. The challenge now is how to shift the whole chip industry into this disaggregated model. It's going to take time, effort, as well as a substantial reali... » read more

3D-IC Reliability Degrades With Increasing Temperature
By Ann Mutschler - 14 Dec, 2022 - Comments: 0

The reliability of 3D-IC designs is dependent upon the ability of engineering teams to control heat, which can significantly degrade performance and accelerate circuit aging. While heat has been problematic in semiconductor design since at least 28nm, it is much more challenging to deal with inside a 3D package, where electromigration can spread to multiple chips on multiple levels. “Be... » read more

Blog Review: Dec. 14
By Jesse Allen - 14 Dec, 2022 - Comments: 0

Siemens EDA's Harry Foster checks out design and verification language adoption trends in FPGA projects, including testbench methodologies and assertion languages. Cadence's Veena Parthan finds that giving electric vehicle batteries a second life as energy storage devices can extend their useful life by 5 to 8 years, but a lack of standardization in EV batteries poses challenges. Synopsys... » read more

Variability Becoming More Problematic, More Diverse
By Karen Heyman - 12 Dec, 2022 - Comments: 0

Process variability is becoming more problematic as transistor density increases, both in planar chips and in heterogeneous advanced packages. On the basis of sheer numbers, there are many more things that can wrong. “If you have a chip with 50 billion transistors, then there are 50 places where a one-in-a-billion event can happen,” said Rob Aitken, a Synopsys fellow. And if Intel’s... » read more

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