tag: DFT

DFTMAX Compression Shared I/O
By Various Writers - 25 Jul, 2013 - Comments: 0

A significant design trend in recent years has been the widespread use of ARM multicore processors in systems-on-chip (SoCs). Designers’ ability to easily and cost-effectively employ multiple, high-performance embedded processors to meet the computational demands of the end application has helped fuel the explosive growth in mobile computing, networking infrastructure, and digital infotainmen... » read more

Observation Post
By Pranav Ashar - 28 Mar, 2013 - Comments: 0

By Pranav Ashar After attending the 2013 Design and Verification Conference (DVCon) in San Jose, Calif., I have compiled notes as both an observer and a panel participant. Here are my observations: Wally Rhines, CEO of Mentor Graphics, gave the keynote presentation: Accelerating EDA Innovation Through SoC Design Methodology Convergence. Logically and effectively he made the case that SoC in... » read more

Making The Right Choices
By Ed Sperling - 21 Feb, 2013 - Comments: 0

FD-SOI at 28nm, or finFETs at 20/14nm? To companies looking at the cost equation, the total market opportunity for SoCs and the NRE required to get there, this is still a manageable formula. It requires lots of number crunching and some unknowns, but by the time you get done with the math it still falls within an acceptable margin of error and the choices are relatively simple. For foundries... » read more

Optimizing Test To Enable Diagnosis-Driven Yield Analysis
By Various Writers - 21 Feb, 2013 - Comments: 0

Using diagnosis-driven yield analysis, companies have decreased their time to yield, managed manufacturing excursions and recovered yield caused by systematic defects. Dramatic time savings and yield gains have been proven using these methods. Companies must plan ahead to take advantage of diagnosis-driven yield analysis. The planning needs to include how and what patterns to generate during AT... » read more

Boosting Yield With Layout Awareness
By Ed Sperling - 26 Apr, 2012 - Comments: 0

By Ann Steffora Mutschler Yield. Just the word can make many engineers cringe and hide in their cubicles—especially with manufacturing problems and excessive power during test increasing causing failures. But the combination of physical data with diagnostics engines may be the light at the end of the tunnel, allowing for easier pinpointing of defects. There are many reasons why a chip fai... » read more

The Hidden Costs Of Test
By Ed Sperling - 06 Oct, 2011 - Comments: 0

By Ed Sperling As complexity grows in SoCs, so does the ability to accurately test them. That helps explain why there are so many different types of tests and so much confusion about what to use to perform those tests, when to test, and where in the flows to include those tests. But what’s less well known is that tests done improperly also can give false results, labeling good chips as bad�... » read more

DFT: Essential For Power-Aware Test
By Ed Sperling - 18 Sep, 2011 - Comments: 0

By Ann Steffora Mutschler Power-aware test is a major manufacturing consideration due to the problems of increased power dissipation in various test modes, as well as test implications that come up with the usage of various low-power design technologies. Challenges for test engineers and test tool developers include understanding the various concerns associated with power-aware test, develo... » read more

Are Test Engineers More Highly Evolved?
By Kiran Vittal - 25 Aug, 2011 - Comments: 0

In a December 2010 blog, my colleague Ron Craig wrote that 94% of respondents to a survey said that timing constraints were a problem. Well, no surprise there. But 70+% said they planned to simply “try harder” during their next project to avoid these problems. Did they really think that was a viable solution? That blog featured a good illustration of the problem. It gave me a good laugh.... » read more

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