tag: DSA

Framework for Prototyping And In-Hardware Evaluation of Post-Quantum Cryptography HW Accelerators (TU Darmstadt)
By Technical Paper Link - 19 Sep, 2023 - Comments: 0

A technical paper titled “PQC-HA: A Framework for Prototyping and In-Hardware Evaluation of Post-Quantum Cryptography Hardware Accelerators” was published by researchers at TU Darmstadt. Abstract: "In the third round of the NIST Post-Quantum Cryptography standardization project, the focus is on optimizing software and hardware implementations of candidate schemes. The winning schemes are ... » read more

Week In Review: Semiconductor Manufacturing, Test
By Gregory Haley - 18 Aug, 2023 - Comments: 0

Intel dropped out of a $5.4 billion deal to purchase Tower Semiconductor in Israel. Intel cited the inability to obtain regulatory approval in a timely manner as the reason for ending the deal signed in February. Intel will pay a $353 million termination fee to Tower. The silicon wafer supply has moved back into positive territory for 2023 thanks to a 7% decline in wafer shipments combined w... » read more

Directed Self-Assembly Finds Its Footing
By Gregory Haley - 17 Aug, 2023 - Comments: 0

Ten years ago, when the industry was struggling to deliver EUV lithography, directed self-assembly (DSA) roared to the forefront of research and development for virtually every manufacturer determined to extend the limits of 193i. It was the hot topic at of the 2012 SPIE Advanced Lithography Conference, with one attendee from Applied Materials comparing its potential to disrupt the industry to ... » read more

Chiplets: Deep Dive Into Designing, Manufacturing, And Testing
By The SE Staff - 07 Aug, 2023 - Comments: 0

Chiplets are a disruptive technology. They change the way chips are designed, manufactured, tested, packaged, as well as the underlying business relationships and fundamentals. But they also open the door to vast new opportunities for existing chipmakers and startups to create highly customized components and systems for specific use cases and market segments. This LEGO-like approach sounds ... » read more

Define & Grow III–V Vertical Nanowires At A High Footprint Density on a Si Platform
By Technical Paper Link - 29 Jul, 2022 - Comments: 0

New technical paper titled "Directed Self-Assembly for Dense Vertical III–V Nanowires on Si and Implications for Gate All-Around Deposition" is published from researchers at Lund University in Sweden. Abstract: "Fabrication of next generation transistors calls for new technological requirements, such as reduced size and increased density of structures. Development of cost-effective proc... » read more

Manufacturing Bits: Nov. 2
By Mark LaPedus - 02 Nov, 2021 - Comments: 0

IRDS lithography roadmap The Journal of Micro/Nanopatterning, Materials, and Metrology (JM3) has published a paper that outlines the lithography roadmap and the various challenges for the next 15 years. The paper, called the "International Roadmap for Devices and Systems lithography roadmap," projects that extreme ultraviolet (EUV) lithography and a next-generation version will remain the m... » read more

ACAP At The Edge With The Versal AI Edge Series
By Xilinx - 30 Jun, 2021 - Comments: 0

This white paper introduces the AI Edge series to the Versal ACAP portfolio, a domain-specific architecture (DSA) that meets the strenuous demands of systems implemented in the 7nm silicon process. This series is optimized to meet the performance-per-watt requirements of edge nodes at or near the analog-digital boundary. Here, immediate response to the physical world is highly valued, and in ma... » read more

Ten Lessons From Three Generations Shaped Google’s TPUv4i
By Technical Paper Link - 11 Jun, 2021 - Comments: 0

Source: Norman P. Jouppi, Doe Hyun Yoon, Matthew Ashcraft, Mark Gottscho, Thomas B. Jablin, George Kurian, James Laudon, Sheng Li, Peter Ma, Xiaoyu Ma, Nishant Patil, Sushma Prasad, Clifford Young, Zongwei Zhou (Google); David Patterson (Google / Berkeley) Find technical paper here. 2021 ACM/IEEE 48th Annual International Symposium on Computer Architecture (ISCA) Abstract–"Google de... » read more

Versal: The First Adaptive Compute Acceleration Platform (ACAP)
By Xilinx - 01 Dec, 2020 - Comments: 0

Recent technical challenges have forced the industry to explore options beyond the conventional “one size fits all” CPU scalar processing solution. Very large vector processing (DSP, GPU) solves some problems, but it runs into traditional scaling challenges due to inflexible, inefficient memory bandwidth usage. Traditional FPGA solutions provide programmable memory hierarchy, but the tradit... » read more

Interconnect Challenges Grow, Tools Lag
By Brian Bailey - 15 Jun, 2020 - Comments: 2

Interconnects are becoming much more problematic as devices shrink and the amount of data being moved around a system continues to rise. This limitation has shown up several times in the past, and it's happening again today. But when the interconnect becomes an issue, it cannot be solved in the same way issues are solved for other aspects of a chip. Typically it results in disruption in how ... » read more

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