IP Integration Challenges Rising

By Ann Mutschler - 24 Jul, 2014 - Comments: 0

It’s not just [getkc id="80" comment="lithography"] that is putting a crimp in sub-28nm designs. As more functions, features, transistors and software are added onto chips, the pressure to get chips out the door has forced chipmakers to lean more heavily on third-party IP providers. Results, as you might expect, have been mixed. The number of blocks has mushroomed, creating its own web of ... » read more

New Winners And Losers

By Brian Bailey - 24 Jul, 2014 - Comments: 0

During DAC 2013, Robert Colwell of DARPA said he was attempting to prepare the U.S. Dept. of Defense for what he believes is the cataclysm caused by the end of [getkc id="74" comment="Moore's Law"]. He asked the question, “What happens when we don’t have a new technology that doubles the number of transistors every couple of years?” Colwell believes that power is the primary reason why... » read more

High-Level Gaps Emerge

By Ann Mutschler - 24 Jul, 2014 - Comments: 0

Semiconductor Engineering sat down to discuss the attributes of a high-level, front-end design flow, and why it is needed at present with Leah Clark, associate technical director for digital video technology at Broadcom; Jon McDonald, technical marketing engineer at Mentor Graphics; Phil Bishop, vice president of the System Level Design System & Verification Group at Cadence; and Bernard Mu... » read more

Reversing Course, With A Twist

By Brian Bailey - 24 Jul, 2014 - Comments: 1

Semiconductor Engineering is running an extended series of articles that examine the assertion that the end of Moore’s Law will have profound implications for the entire semiconductor, EDA and IP industries. Part one of this article, which focuses on the EDA industry, addressed the question about who was going to pay for future development of EDA tools for the latest production nodes. The ind... » read more

It’s Time to Bring GDS “Reality” Into Routing Closure

By Jean-Marie Brunet - 17 Jul, 2014 - Comments: 0

By Nancy Nguyen and Jean-Marie Brunet Imported cells, whether macros, standard cells, or intellectual property (IP), are a common element of today’s integrated circuit (IC) designs. Historically, when designers incorporate these cells into a design, they import them using an abstract format defined by a layout exchange format (LEF) file. This abstract view provides basic information about th... » read more

EDA Tools, IP Sales Up

By Ed Sperling - 15 Jul, 2014 - Comments: 0

EDA sales grew 4.6% in the first quarter, down slightly year-over-year as sales in Japan dragged down the rest of the market. Sales in Japan dropped 19% year over year as the country’s electronics industry struggles for footing against rivals in China and South Korea. North America and Europe grew 7% and 7.5% respectively, according to statistics provided by the EDA Consortium. Within thos... » read more

The Week In Review: Design

By Ed Sperling - 11 Jul, 2014 - Comments: 0

M&A CEVA bought RivieraWaves, which makes IP for WiFi and Bluetooth connectivity. CEVA said the deal will boost its market to 35 billion connected devices within six years. The two companies have been collaborating in the WiFi market for the past couple of years. Total cost of the deal is $19 million. Mentor Graphics acquired XS Embedded GmbH, a German-based developer of automotive-read... » read more

IP And FinFETs At Advanced Nodes

By Ed Sperling - 10 Jul, 2014 - Comments: 2

Semiconductor Engineering sat down to discuss IP and finFETs at advanced nodes with Bernard Murphy, CTO of Atrenta; Warren Savage, president and CEO of IPextreme; Aveek Sarkar, vice president of engineering and product support at Ansys-Apache; Randy Smith, vice president of marketing at Sonics. What follows are excerpts of that conversation. SE: As we push into the next nodes, we’ve got a ... » read more

Ultra Low-Power 9D Sensor Fusion Implementation

By Synopsys - 09 Jul, 2014 - Comments: 0

This paper presents a case study on computing the 3D orientation of a device by means of a 9D fusion algorithm. The focus is on optimizing the fusion algorithm for execution on the DesignWare Sensor IP Subsystem. Performance measurements show the benefits of using ARC Processor EXtension (APEX) accelerators, which improve both cycle count and energy consumption in comparison to other commercial... » read more

R-FPGA Security Risks

By Ernest Worthman - 07 Jul, 2014 - Comments: 0

Configurable chips have been around for a long time. Modern FPGAs, E/EEPROMS and other types of programmable memory have allowed us some flexibility in changing chip functionality in the field. But really, this is static reprogramming and requires a process and procedure. Moreover, it needs to done by knowledgeable programmers, either on site or remotely. But the fact remains that field re-prog... » read more

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Knowledge Centers
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