tag: IP

The Week In Review: Design
By Ed Sperling - 21 Mar, 2014 - Comments: 0

Tools Mentor Graphics unveiled a new version of its PCB design platform, even going so far as to rename it slightly (Expedition to Xpedition). Mentor claims it’s the most significant product in that space in years, bridging the environments between designers and engineers. Included are placement planning in densely packed boards, which simplifies re-use and improves time to market, and elect... » read more

Big Shift In SoC Verification
By Ed Sperling - 17 Mar, 2014 - Comments: 2

Semiconductor Engineering sat down to discuss software-driven verification with Ken Knowlson, principal engineer at Intel; Mark Olen, product manager for the Design Verification Technology Division of Mentor Graphics; Steve Chappell, senior manager for CAE technology and verification at Synopsys; Frank Schirrmeister, group director for product marketing of the System Development Suite at Cadenc... » read more

More Pain In More Places
By Ed Sperling - 14 Mar, 2014 - Comments: 2

Pain is nothing new in to the semiconductor industry. In fact, the pain of getting complex designs completed on budget, and finding the bugs in those designs, has been responsible for decades of continuous growth in EDA, IP, test, packaging, and foundries. But going forward there is change afoot in every segment of the flow from architecture to design to layout to verification to manufacturi... » read more

The Week In Review: Design
By Ed Sperling - 14 Mar, 2014 - Comments: 0

Tools Synopsys uncorked the next version of its verification tool, which includes static and formal verification, new debug capabilities, and low-power and X-propagation simulation. The company says the new tool offers up to 5X performance improvement. Cadence rolled out a new version of its verification solution for designs using ARM’s interconnect IP, speeding up verification and analys... » read more

Do We Need A “Glue” Engineer?
By Brian Fuller - 13 Mar, 2014 - Comments: 0

Design and verification are so complex today and fraught with market risk that it keeps managers awake and sweating at night. So much of design is carved up in IP blocks and subsystems, each with their own verification issues and methodologies. To manage the complexity the design is partitioned, and so too are the teams. But as software verification becomes more crucial to system-design succ... » read more

Design Guidelines For Embedded Real Time Face Detection Application
By Various Writers - 12 Mar, 2014 - Comments: 0

This paper presents steps for real-time deployment of face detection application on a programmable vector processor. The steps taken are general purpose in the sense that they can be used to implement similar computer vision algorithms on any mobile device. To download this white paper, click here. » read more

USB 3.1: Evolution And Revolution
By Various Writers - 12 Mar, 2014 - Comments: 0

USB-IF Worldwide Developers Days introduced developers to the new USB 3.1 specification. On the surface, USB 3.1 seems like it could be only an update to 10G speeds, but this white paper will dig deeper into 10G USB 3.1 to clarify the evolutionary and revolutionary changes in the USB 3.1 specification. USB 3.1 introduces a new 10 Gbps signaling rate in addition to the 5 Gbps signaling rate defi... » read more

SoC Integration Mistakes
By Ed Sperling - 10 Mar, 2014 - Comments: 0

Semiconductor Engineering sat down to discuss integration challenges with Ruggero Castagnetti, distinguished engineer at LSI; Rob Aitken, an ARM fellow; Robert Lefferts, director of engineering in Synopsys’ Solutions Group; Bernard Murphy, chief technology officer at Atrenta; and Luigi Capodieci, R&D fellow at GlobalFoundries. What follows are excerpts of that roundtable discussion. S... » read more

EDA Hungers For Growth
By Brian Bailey - 27 Feb, 2014 - Comments: 1

Look at the top line numbers provided by the EDA industry consortium (EDAC) and it appears as if the industry is doing well. In 2010, revenue was $5.285 billion. That number increased to $6.218 billion in 2011, and again to $6.529 billion in 2012, a 9.5% annual growth rate that would satisfy most investors. But the numbers do not tell the whole story. There is an interesting divide growing betw... » read more

SoC Integration Mistakes
By Ed Sperling - 26 Feb, 2014 - Comments: 1

Semiconductor Engineering sat down to discuss integration challenges with Ruggero Castagnetti, distinguished engineer at LSI; Rob Aitken, an ARM fellow; Robert Lefferts, director of engineering in Synopsys’ Solutions Group; Bernard Murphy, chief technology officer at Atrenta; and Luigi Capodieci, R&D fellow at GlobalFoundries. What follows are excerpts of that roundtable discussion. S... » read more

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