tag: IP

Experts At The Table: Yield And Reliability Issues With Integrating IP
By Ed Sperling - 08 Jan, 2014 - Comments: 0

Semiconductor Engineering sat down to discuss the impact of integrating IP in complex SoCs with Juan Rey, senior director of engineering at Mentor Graphics; Kevin Yee, product marketing director for Cadence’s SoC Realization Group; and Mike Gianfagna, vice president of marketing at eSilicon. What follows are excerpts of that conversation. SE: Do we need to move to subsystems or more restri... » read more

Tech Talk: FPGA Prototyping
By Ed Sperling - 03 Jan, 2014 - Comments: 0

Neil Songcuan, senior product marketing manager at Synopsys, examines the hidden time savings from using an FPGA prototype platform for IP validation and software development, in addition to hardware design. While FPGA prototypes are a well known way of speeding up hardware design, their value in IP validation and software development for an integrated SoC is just beginning to surface. [you... » read more

The End Is Near
By Ed Sperling - 30 Dec, 2013 - Comments: 0

Looking back is easier than looking forward, and looking narrow is easier than looking wide. In 2013, there were several fundamental changes. Change No. 1: IP is now a lucrative market. From Synopsys’ standpoint, it’s been a lucrative market for some time. But the acquisitions made by Cadence, beginning in late 2012, coupled with the push by ARM into the micro-server market and the flail... » read more

When Is Verification Done?
By Ed Sperling - 20 Dec, 2013 - Comments: 0

Verification is becoming much more difficult at 16nm/14nm, driven by the sheer complexity of SoCs, the fact that there is much more to verify, and the impact of physical effects, which now affect what used to be exclusively the realm of functional verification. The questions these changes raise are daunting, and for many engineers rather unnerving. The whole validation, verification and debu... » read more

Week In Review: System-Level Design
By Ed Sperling - 20 Dec, 2013 - Comments: 0

Synopsys extended its FPGA prototyping board with a new version that is optimized for IP and subsystems. This is particularly interesting given the fact that Synopsys is one of the largest IP providers and currently sells subsystems based on its ARC processor IP. Among the new features are support for 4 million gates for software development and hardware-software integration, as well as synthes... » read more

Where Is 2.5D?
By Ed Sperling - 19 Dec, 2013 - Comments: 3

After nearly five years of concentrated research, development, test chips and characterization, 2.5D remains a possibility for many companies but a reality for very few. So what’s taking so long and why hasn’t all of this hype turned into production runs instead of test chips? Semiconductor Engineering spent the past two months interviewing dozens of people on this subject, from chipmakers ... » read more

Can Intel Dethrone The Foundry Giants?
By Mark LaPedus - 12 Dec, 2013 - Comments: 3

The leading-edge foundry business isn’t for the faint of heart. It requires deep pockets and sound technology to keep pace in the chip-scaling race. And despite pouring billions of dollars into new fabs and processes, foundries are competing for fewer customers at each node. Given the difficult business conditions, only a handful of vendors can afford to compete in the high-end foundry bus... » read more

Experts At The Table: Yield And Reliability Issues With Integrating IP
By Ed Sperling - 12 Dec, 2013 - Comments: 0

Semiconductor Engineering sat down to discuss the impact of integrating IP in complex SoCs with Juan Rey, senior director of engineering at Mentor Graphics; Kevin Yee, product marketing director for Cadence’s SoC Realization Group; and Mike Gianfagna, vice president of marketing at eSilicon. What follows are excerpts of that conversation. SE: As more pieces are integrated into complex SoCs... » read more

Experts At The Table: What’s Missing In The IoT
By Ed Sperling - 11 Dec, 2013 - Comments: 0

Semiconductor Engineering sat down to discuss the future of the IoT with Oleg Logvinov, director of market development for STMicroelectronics’ Industrial and Power Conversion Division; Martin Lund, senior vice president of the IP Group at Cadence; Naveed Sherwani, president and CEO of Open-Silicon; and Damon Hernandez, a member of the Web3D Consortium. What follows are excerpts of that conver... » read more

New Challenges Emerge With FinFETs
By Ed Sperling - 05 Dec, 2013 - Comments: 0

Working at advanced process nodes is always tricky. There are new things to worry about and more rules to deal with initially, yet the promised benefit is improved performance, power and area, or cost. But at the next process node, and the one after that, there are so many variables coming into play that trying to make sense of the PPA equation is becoming much more difficult. Early reports ... » read more

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