tag: lithography

Manufacturing Bits: Dec. 2
By Mark LaPedus - 02 Dec, 2014 - Comments: 0

Storage ring EUV source Needless to say, extreme ultraviolet (EUV) lithography is delayed. Chipmakers hope to insert EUV at the 7nm node, but that’s not a given. As before, the big problem is the EUV light source. So far, the source can’t generate enough power to enable the required throughput for EUV in mass production. Researchers at the SLAC National Accelerator Laboratory have one p... » read more

Design Rules Explode At New Nodes
By Ed Sperling - 17 Nov, 2014 - Comments: 0

Semiconductor Engineering sat down changing design rules with Sergey Shumarayev, senior director of custom IP design at Altera; Luigi Capodieci, R&D fellow at [getentity id="22819" comment="GlobalFoundries"]; Michael White, director of product marketing for Calibre Physical Verification at [getentity id="22017" e_name="Mentor Graphics"], and Coby Zelnik, CEO of [getentity id="22478" e_name=... » read more

Photoresist Problems Ahead
By Ann Mutschler - 14 Nov, 2014 - Comments: 2

As the semiconductor industry begins its ramp to manufacturing at 10nm and below, activity is heating up involving lithography modeling. The goal is to be ready when all the pieces of the puzzle are in place. That includes [gettech id="31045" comment="EUV"], when it finally becomes commercially viable, as well as extending ArF [getkc id="80" comment="lithography"]. When it comes to lithogra... » read more

Future Directions Unknown
By Ed Sperling - 13 Nov, 2014 - Comments: 0

The semiconductor industry has been on cruise control when it comes to shrinking features, but as process technology progresses to 10nm and 7nm there will be some significant changes. For one thing, the cost per new design will continue to rise, which means only the largest companies with the biggest market opportunity will be able to invest at the leading-edge nodes. Chips for mobile phones... » read more

Transistor Options Narrow For 7nm
By Mark LaPedus - 13 Nov, 2014 - Comments: 0

Chipmakers are currently ramping up silicon-based finFETs at the 16nm/14nm node, with plans to scale the same technology to 10nm. Now, the industry is focusing on the transistor options for 7nm and beyond. At one time, the leading contenders involved several next-generation transistor types. At present, the industry is narrowing down the options and one technology is taking a surprising lea... » read more

EUV Still Matters…But Less
By Ed Sperling - 16 Oct, 2014 - Comments: 0

For all the chatter and occasional tirades about EUV missing its market window—it's true, EUV will have missed five market windows by 10nm—it still matters. And the sooner EUV hits the market with a viable power source, the better off the entire semiconductor manufacturing industry will be. But even EUV is a sideshow to some important shifts underway in technology. While technologically ... » read more

Litho Options Sparse After 10nm
By Mark LaPedus - 16 Oct, 2014 - Comments: 0

Leading-edge foundries are ramping up their 16nm/14nm logic processes, with 10nm and 7nm in R&D. Barring a major breakthrough in [getkc id="80" comment="lithography"], chipmakers will use 193nm immersion and multiple patterning for both 16nm/14nm and 10nm. So now, chipmakers are focusing on the lithography options for 7nm. As before, the options include the usual suspects—[gettech id="... » read more

The Impact Of 14nm Photomask Uncertainties On Computational Lithography Solutions
By Mentor, a Siemens Business - 16 Oct, 2014 - Comments: 0

Computational lithography solutions rely upon accurate process models to faithfully represent the imaging system output for a defined set of process and design inputs. These models, in turn, rely upon the accurate representation of multiple parameters associated with the scanner and the photomask. While certain system input variables, such as scanner numerical aperture, can be empirically tuned... » read more

Executive Insight: Lip-Bu Tan
By Ed Sperling - 22 Sep, 2014 - Comments: 0

Semiconductor Engineering sat down with [getperson id="11693" comment="Lip-Bu Tan"], president and CEO of [getentity id="22032" e_name ="Cadence"], to discuss his outlook on EDA, Moore’s Law and his strategy for investing in startups around the world. What follows are excerpts of that conversation. SE: What’s worrying you these days? Tan: There are a couple of things. One is the complex... » read more

2014 eBeam Survey Results
By eBeam Initiative - 18 Sep, 2014 - Comments: 0

An industry-wide poll highlights what the industry is thinking about EUV and mask writing at advanced nodes. To view the poll, click here. » read more

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