tag: lithography

Experts At The Table: Issues In Lithography
By Ed Sperling - 29 Oct, 2012 - Comments: 0

By Mark LaPedus Semiconductor Manufacturing & Design sat down to discuss future lithography challenges with Juan Rey, senior director of engineering at Mentor Graphics; Aki Fujimura, chairman and chief executive at D2S; and Tatsuo Enami, general manager for the sales division at Gigaphoton. What follows are excerpts of that conversation. (Part one can be found here.) SMD: Let’s re-vi... » read more

Experts At The Table: Issues In Lithography
By Ed Sperling - 18 Oct, 2012 - Comments: 0

By Mark LaPedus Semiconductor Manufacturing & Design sat down to discuss future lithography challenges with Juan Rey, senior director of engineering at Mentor Graphics; Aki Fujimura, chairman and chief executive at D2S; and Tatsuo Enami, general manager for the sales division at Gigaphoton. What follows are excerpts of that conversation. SMD: What are the big challenges in lithography?... » read more

ASML to Buy Cymer
By Chris Mack - 17 Oct, 2012 - Comments: 0

"We have experienced some delay in EUV, basically caused by delays in developing the light source", said Peter Wennink, ASML's financial chief. With that understatement, ASML succinctly explained its rationale for offering $2.6B in cash (25%) and stock (75%) to buy San Diego-based Cymer, the leading developer of EUV sources.  Over the last year, ASML has sent about 500 of their engineers to... » read more

A Mischievous Muse
By Marc David Levenson - 20 Sep, 2012 - Comments: 0

By Marc David Levenson Moorissa, the muse of high technology, enjoys playing practical jokes on the mask-makers, whose annual meeting was the week of Sept. 10 in Monterey. It started long ago…For example, no sooner had mask makers learned how to write precise 1X masks with fancy electron beams than the wafer printing industry went to reduction steppers, negating the advantages of all that pr... » read more

A Hybrid Model/Pattern-Based OPC Approach For Improved Consistency And TAT
By Various Writers - 20 Sep, 2012 - Comments: 0

As the technology advances, OPC run time turns to be a big concern, and a great deal of our effort is directed toward speeding up the litho operations. In addition, the OPC simulation consistency sometimes deteriorates, which is a critical issue—especially for anchor features. On the other hand, full-chip designs usually comprise large arrays of basic cells, used by OPC engineers to tune OPC ... » read more

There’s More To EUV Than Source Power
By Katherine Derbyshire - 20 Sep, 2012 - Comments: 0

By Katherine Derbyshire For some time now, most industry coverage of EUV lithography has focused on the light source. As my colleagues have pointed out, source power limitations impose major constraints on not only potential EUV-based device manufacturing, but even on development of sub-20nm devices and process technologies. When throughput is in the neighborhood of four wafers per hour, lear... » read more

Inflection Points Ahead
By Ed Sperling - 23 Aug, 2012 - Comments: 0

By Ed Sperling Engineering challenges have existed at every process node in semiconductor designs, but at 20nm and beyond, engineers and executives on all sides of the industry are talking about inflection points. An inflection point is literally the place where a curve on a graph turns down or up, but in the semiconductor industry it’s usually associated with the point at which a progres... » read more

Why the Big Players Like 450mm Wafers
By Chris Mack - 20 Aug, 2012 - Comments: 0

The reason semiconductor manufacturers like the idea of 450-mm wafers is easy to understand:  bigger wafers should lower the per-chip cost of manufacturing.  But as I mentioned in my last post, this per-chip cost advantage doesn’t apply to lithography.  Each time a wafer size is increased, only the non-litho (per-chip) costs go down, and so lithography costs take up a bigger portion of the... » read more

Experts At The Table: Challenges At 20nm
By Ed Sperling - 17 Aug, 2012 - Comments: 0

By Ed Sperling Low-Power/High-Performance Engineering sat down to discuss the challenges at 20nm and beyond with Jean-Pierre Geronimi, special projects director at STMicroelectronics; Pete McCrorie, director of product marketing for silicon realization at Cadence; Carey Robertson, director of product marketing at Mentor Graphics; and Isadore Katz, president and CEO of CLK Design Automation. Wh... » read more

Experts At The Table: Challenges At 20nm
By Ed Sperling - 17 Aug, 2012 - Comments: 0

By Ed Sperling Low-Power/High-Performance Engineering sat down to discuss the challenges at 20nm and beyond with Jean-Pierre Geronimi, special projects director at STMicroelectronics; Pete McCrorie, director of product marketing for silicon realization at Cadence; Carey Robertson, director of product marketing at Mentor Graphics; and Isadore Katz, president and CEO of CLK Design Automation. Wh... » read more

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