tag: Mentor Graphics

More Simplicity Next Year
By Anne Cirkel - 20 Jun, 2014 - Comments: 0

I briefly mentioned last week that I want to give you a glimpse behind the curtain of the DAC operation during the year. One goal of this blog is to give you some insight into the work the fabulous volunteers for DAC are doing. And that’s not only the 20 volunteers on the DAC Executive Committee. From the technical program committees all the way to the marketing committee, the event is entire... » read more

Designing And Testing FinFET-based IC Designs
By Mentor Graphics Staff Writers - 19 Jun, 2014 - Comments: 0

By Carey Robertson and Steve Pateras The emergence of FinFET transistors has had a significant impact on the IC physical design and design-for-test flows. The introduction of FinFETs means that CMOS transistors must be modeled as three-dimensional (3D) devices during the IC design process, with all the complexity and uncertainty this entails. The BSIM Group of the UC Berkeley Device Group has ... » read more

Root Cause Deconvolution
By Mentor, a Siemens Business - 19 Jun, 2014 - Comments: 0

Scan logic diagnosis turns failing test cycles into valuable data and is an established method for digital semiconductor defect localization. The advent of layout-aware scan diagnosis represented a dramatic advance in diagnosis technology because it reduces suspect area by up to 85% and identifies physical net segments rather than entire logic nets [1-3]. The defect classifications provided by ... » read more

Is The Definition Of IC Reliability Changing?
By Matthew Hogan - 18 Jun, 2014 - Comments: 1

“You know, brain surgery's not difficult if you don't care whether the person dies, it's actually quite easy. Flying a plane is quite easy if you don't mind crashing. That's what hard means. It's an expression of how much you care about the result. And if you are proud of it, or you believe it can be good and you want it to be good, then it can be sort of infinitely hard, to the point where i... » read more

Blog Review: June 18
By Ed Sperling - 18 Jun, 2014 - Comments: 1

Mentor’s Vern Wnek recalls “a living hell” of being trapped in a small office for three weeks with a PCB designer who ate too much garlic and sweated profusely. This could be a reality TV series. What do engineers really think about UVM? Cadence's Richard Goering braved a 7 a.m. breakfast at DAC to hear a panel of experts, including reps from Intel, Ericsson, Imagination and Freescale,... » read more

New Uses For Emulation
By Ed Sperling - 16 Jun, 2014 - Comments: 1

Semiconductor Engineering sat down to discuss the changing emulation landscape with Jim Kenney, director of marketing for emulation at Mentor Graphics; Tom Borgstrom, director of the verification group at Synopsys; Frank Schirrmeister, group director of product marketing for the System Development Suite at Cadence; Gary Smith, chief analyst at Gary Smith EDA; and Lauro Rizzatti, a verification ... » read more

Kicking Off DAC 2015
By Anne Cirkel - 13 Jun, 2014 - Comments: 2

The DAC executive committee closed the 51st DAC last Friday. And guess what? Right afterward we had the first planning meeting for next year’s conference, for which I’ll serve as General Chair. Because most attendees don’t really get a glimpse behind the curtain into these sorts of activities, I thought I’d experiment by blogging my way to next June in San Francisco. I plan to publis... » read more

The Week In Review: Design
By Ed Sperling - 13 Jun, 2014 - Comments: 0

Tools Mentor Graphics uncorked a tool for IC, package and board optimization, assembly and visualization. Of particular note is a “virtual die model” capability, which can be used across multiple domains in the design process. Deals Rambus inked a patent licensing agreement with Qualcomm Global Trading, a subsidiary of Qualcomm, for memory, interface and security technologies. The secu... » read more

S-L Power Modeling Gains Steam
By Ann Mutschler - 12 Jun, 2014 - Comments: 1

Power analysis, architectural exploration and optimization of an SoC is a hot topic of discussion today. It is well accepted this must be addressed at a higher level of abstraction because not just the hardware must be taken into account with power intent and power management structures. It has to be viewed from a system point of view, as well, where the hardware resides along with the opera... » read more

As Nodes Advance, So Must Power Analysis
By Mentor, a Siemens Business - 12 Jun, 2014 - Comments: 0

By Chetandeep Singh and Ravi Tangirala Smaller geometry nodes offer cost and performance advantages that encourage their adoption. Yet they present a new set of challenges for IC manufacturers: Though transistors are smaller, they leak more current. This is an important issue as the demand for high-performance, battery-operated, system-on-chips (SoC) in communication and computing shifts th... » read more

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