tag: Mentor Graphics

Is Art Acceptable In Verification?
By Brian Bailey - 23 Apr, 2015 - Comments: 0

The industry appears to have accepted that [getkc id="10" kc_name="verification"] involves art as well as science. This is usually based on one of three reasons, namely: the problem is large and complex; there is a lack of understanding and tools that enable it to be automated; and if it could be made a science, all of the jobs would have migrated offshore. Today, designs are built from pre-... » read more

Partly Sunny, With A Chance For Explosive Growth
By Mike Gianfagna - 23 Apr, 2015 - Comments: 0

I recently attended a session at the Mentor Graphics User Conference (User2User) in San Jose that dealt with the changing foundry landscape. The session was moderated by SemiWiki's Dan Nenni and included: • Giorgio Cesana, director of technology at STMicroelectronics • Jack Harding, co-founder, president & CEO of eSilicon • Lluis Paris, deputy director of worldwide IP alliances at ... » read more

Pressure Builds To Revamp The Design Flow
By Ed Sperling - 23 Apr, 2015 - Comments: 1

Without [getkc id="7" kc_name="EDA"] there would be no [getkc id="74" comment="Moore's Law"] as we know it today, and without Moore's Law there would be a much more limited need for EDA. But after more than three decades of developing design flows packed with sophisticated tools to automate semiconductor design through verification, and thereby enable feature shrinks that are the basis of Moore... » read more

Blurring The Lines On Prototyping
By Ann Mutschler - 23 Apr, 2015 - Comments: 0

Prototyping is an integral part of every [getkc id="81" kc_name="SoC"] today, with two main approaches being used: virtual or software-based, and physical, which includes FPGA-based boards as well as hardware emulation systems. [getkc id="104" kc_name="Virtual prototyping"] is typically used for software development in the early stages of SoC design, even before SoC [getkc id="49" kc_name="R... » read more

High-Performance Analog And RF Circuit Simulation Using The Analog FastSPICE Platform At Columbia University
By Mentor, a Siemens Business - 22 Apr, 2015 - Comments: 0

The research group led by Professor Peter Kinget at the Columbia University Integrated Systems Laboratory (CISL) focuses on cutting edge analog and RF circuit design using digital nanoscale CMOS processes. Areas of research include design techniques for circuits operating below 1 V, digitally calibrated RF front ends for superior linearity performance, LO synthesizers for wireless applications,... » read more

Blog Review: April 22
By Jesse Allen - 22 Apr, 2015 - Comments: 0

DARPA thinks machine-brain interfaces are poised to become an industry-changing technology. Rambus' David G. Stork brings us emerging developments in the field from the Neural Engineering Boot Camp. If you live in an area that doesn't get quite enough sun for solar panels, how about a smart window that harvests energy from wind and rain? In this week's top five picks, Ansys' Justin Nescott a... » read more

Week 45: 7 Weeks To DAC
By Anne Cirkel - 17 Apr, 2015 - Comments: 0

Make sure to download and use the mobile app for #52DAC this year. It will make your time at the conference a lot easier and should even bring you a bit of fun — and a chance to win a new Apple watch. This year the app includes a game called DAC Attack. No, you don’t score by throwing virtual tomatoes at the executive committee, though we can help you rack up points. (More on this in a b... » read more

Are Three Eyes Better Than Two?
By David Abercrombie - 16 Apr, 2015 - Comments: 0

It is clear that having two eyes is better than having just one. Not only is depth perception much better, but we get to enjoy 3D movies because of it. There is also some sense of security in knowing that if something terrible happened to one eye, you always have a backup. Have you ever wondered if these sorts of advantages are extendable? You’ve probably heard the phrase about someone ha... » read more

Big Changes At 10nm And Beyond
By Ed Sperling - 16 Apr, 2015 - Comments: 0

The move to 16/14nm finFETs is relatively straightforward. The move to 10nm and 7nm will be quite different. While double patterning with colors at 16/14nm has a rather steep learning curve, reports from chipmakers developing advanced chips is the technology and methodologies are manageable once engineering teams begin working with it. The hardest part is visualizing how different parts will... » read more

New Patterning Paradigm?
By Mark LaPedus - 16 Apr, 2015 - Comments: 0

Chip scaling is becoming more difficult at each process node, but the industry continues to find new and innovative ways to solve the problems at every turn. And so chipmakers continue to march down the various process nodes. But the question is for how much longer? In fact, at 16nm/14nm and beyond, chipmakers are finding new and different challenges, which, in turn, could slow IC scaling or br... » read more

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