tag: Mentor Graphics

Chip-Package-Board Optimization: The Future Of Integrated Co-Design
By John Park - 26 Mar, 2015 - Comments: 0

Multi-die and three-dimensional packages have made breakout and routing of extremely high-pin-count devices on PCBs very difficult. Keeping track of all the signals and pins is also a task that has just about outgrown current methods. Many companies simply use a spreadsheet for tracking signals. With no central database or accurate device modeling and rule-based optimization, design intent is o... » read more

DDR4 Board Design And Signal Integrity Verification Challenges
By Mentor, a Siemens Business - 25 Mar, 2015 - Comments: 0

This paper, originally presented at DesignCon and nominated for a best paper award, includes an investigation of DDR4's Pseudo Open Drain driver and what its use means for power consumption and Vref levels for the receivers. This paper also examines a DDR4 system design example and the need for simulating with IBIS power aware models versus transistor level models for Simultaneous Switching ... » read more

Blog Review: March 25
By Jesse Allen - 25 Mar, 2015 - Comments: 0

From brain implants that recover memories to color-shifting shoes, Ansys' Bill Vandermark features sci-fi visions of the future that are becoming reality in his top five tech picks of the week. In the world of embedded software, is a black box better? Mentor's Colin Walls questions whether the advantages that come of having full access to source code outweigh the downsides. Cadence's Neel... » read more

Week 41: The Rise Of Security At DAC
By Anne Cirkel - 20 Mar, 2015 - Comments: 0

All potential attendees interested in security topics should know one thing—the Wednesday keynote on hacking automobiles, while sure to be compelling, will only scratch the surface of security-related content at DAC. Another presenter will talk about how increasing demand for “connected life on the go” and “Internet-enabled everything” opens up a wide variety of security issues for Io... » read more

The Week In Review: Design/IoT
By Jesse Allen - 20 Mar, 2015 - Comments: 0

Mergers & Acquisitions Silvaco acquired Invarian, anticipating integration of Invarian's methodology will accelerate adoption of concurrent power-voltage-thermal analysis. Legal A U.S. District Court judge ordered Kilopass to pay $5.5 million to Sidense for legal fees incurred in Kilopass' patent infringement suit against Sidense. That lawsuit was  dismissed in 2012. Sidense filed... » read more

3D Effects At 20nm And Beyond
By Ann Mutschler - 19 Mar, 2015 - Comments: 0

At the 20nm process node and below, attenuated phase shift masks (PSM) are used in the photolithography process, which results in approximately 70nm of topography. This now must be accounted for using 3D mask approximation. Aki Fujimura, CEO of [getentity id="22864" comment="D2S"], explained that in terms of [getkc id="80" comment="lithography"], where simulation-based technologies are used,... » read more

Migrating Consumer Electronics To The Automotive Market With Calibre PERC
By Mentor, a Siemens Business - 19 Mar, 2015 - Comments: 0

Tough reliability standards for electronic automotive safety systems ensure that integrated circuits (ICs) for these systems comply with demanding performance and reliability requirements. However, companies seeking to leverage their consumer-based intellectual property (IP) for use in automotive “infotainment” and “connected car” applications are finding that many of these performance ... » read more

Capacity Constraints And DFM At Mature Nodes
By Jeff Wilson - 19 Mar, 2015 - Comments: 0

We’re witnessing an interesting phenomenon in the SoC segment of the semiconductor industry today. One might call it the “forced waterfall effect.” What I’m referring to is the tendency for production at semiconductor nodes older than the leading edge to be under long-term foundry capacity constraints. Normally this occurs with the “hot process node,” that is, the leading edge wh... » read more

Blog Review: March 18
By Jesse Allen - 18 Mar, 2015 - Comments: 0

How do you quantify effort spent in FPGA verification? Mentor's Harry Foster tackles the question in his latest installment of the Wilson Research Group functional verification study. A new frontier of design challenges is rapidly emerging, according to ARM CEO Simon Segars. Cadence's Brian Fuller brings us his keynote address at CDNLive. Synopsys' Tushar Mattu is back with more on AXI VI... » read more

First Time Success And Cost Control
By Brian Bailey - 13 Mar, 2015 - Comments: 0

First time success has been the ultimate goal for semiconductor companies due to escalating mask costs, as well as a guiding objective for the development of EDA tools, especially in the systems and verification space. These pressures are magnified for the [getkc id="76" comment="Internet of Things"] (IoT), especially the edge devices. Have system-level tools been able to contribute to first ti... » read more

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