tag: Moore’s Law

MIT: Computing Power Impact on 5 Domains
By Technical Paper Link - 13 Jul, 2022 - Comments: 0

New technical paper titled "The Importance of (Exponentially More) Computing Power" from researchers at MIT CSAIL and Sloan School of Management. Abstract "Denizens of Silicon Valley have called Moore's Law "the most important graph in human history," and economists have found that Moore's Law-powered I.T. revolution has been one of the most important sources of national productivity growth... » read more

What Future Processors Will Look Like
By Ed Sperling - 13 Jul, 2022 - Comments: 0

Mark Papermaster, CTO at AMD, sat down with Semiconductor Engineering to talk about architectural changes that are required as the benefits of scaling decrease, including chiplets, new standards for heterogeneous integration, and different types of memory. What follows are excerpts of that conversation. SE: What does a processor look like in five years? Is it a bunch of chips in a package? I... » read more

Standardizing Chiplet Interconnects
By John Koon - 23 May, 2022 - Comments: 0

The chip industry is making progress on standardizing the infrastructure for chiplets, setting the stage for faster and more predictable integration of different functions and features from different vendors. The ability to choose from a menu of small, highly specialized chips, and to mix and match them for specific applications and use cases, has been on the horizon for more than a decade. ... » read more

New End Markets, More Demand For Complex Chips
By Ed Sperling - 16 May, 2022 - Comments: 0

Experts at the Table: Semiconductor Engineering sat down to discuss economic conditions and how that affects chip design with Anirudh Devgan, president and CEO of Cadence; Joseph Sawicki, executive vice president of Siemens EDA; Niels Faché, vice president and general manager at Keysight; Simon Segars, advisor at Arm; and Aki Fujimura, chairman and CEO of D2S. This discussion was held in front... » read more

More Options, Less Dark Silicon
By Ed Sperling - 20 Apr, 2022 - Comments: 0

Chipmakers are beginning to re-examine how much dark silicon should be used in a heterogenous system, where it works best, and what alternatives are available — a direct result of a slowdown in Moore's Law scaling and the increasing disaggregation of SoCs. The concept of dark silicon has been around for a couple decades, but it really began taking off with the introduction of the Internet ... » read more

Planning EDA’s Next Steps
By Ed Sperling - 24 Mar, 2022 - Comments: 0

Anirudh Devgan, Cadence's new CEO, and the recipient of the Phil Kaufman Award in December, sat down with Semiconductor Engineering to talk about what's next in EDA, the underlying technology and business challenges and changes, and new markets that are unfolding for floor-planning, verification, CFD, and advanced packaging. SE: Where does EDA need to improve? Devgan: We have made it much... » read more

Which Processor Is Best?
By Ed Sperling - 01 Mar, 2022 - Comments: 2

Intel's embrace of RISC-V represents a landmark shift in the processor world. It's a recognition that no single company can own the data center anymore, upending a revenue model that has persisted since the earliest days of computing. Intel gained traction in that market in the early 1990s with the explosion of commodity servers, but its role is changing as processors become more customized and... » read more

Improving PPA In Complex Designs With AI
By John Koon - 14 Feb, 2022 - Comments: 0

The goal of chip design always has been to optimize power, performance, and area (PPA), but results can vary greatly even with the best tools and highly experienced engineering teams. Optimizing PPA involves a growing number of tradeoffs that can vary by application, by availability of IP and other components, as well as the familiarity of engineers with different tools and methodologies. Fo... » read more

Photomask Challenges At 3nm And Beyond
By Mark LaPedus - 25 Jan, 2022 - Comments: 1

Experts at the Table: Semiconductor Engineering sat down to discuss optical and EUV photomasks issues, as well as the challenges facing the mask business, with Naoya Hayashi, research fellow at DNP; Peter Buck, director of MPC & mask defect management at Siemens Digital Industries Software; Bryan Kasprowicz, senior director of technical strategy at Hoya; and Aki Fujimura, CEO of D2S. What f... » read more

Domain-Specific Design Drives EDA Changes
By Ann Mutschler - 03 Jan, 2022 - Comments: 0

The chip design ecosystem is beginning to pivot toward domain-specific architectures, setting off a scramble among tools vendors to simplify and optimize existing tools and methodologies. The move reflects a sharp slowdown in Moore's Law scaling as the best approach for improving performance and reducing power. In its place, chipmakers — which now includes systems companies — are pushing... » read more

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