tag: test

Packetized Scan Test Delivery
By Geir Eide - 06 Jul, 2021 - Comments: 0

The traditional approach to moving scan test data from chip-level pins to core-level scan channels is under pressure due to the dramatic rise in design size, design complexity, and test adaptation. To address these challenges, we now have the option of implementing a packetized data network for scan test that moves the scan data through the SoC much more efficiently than the traditional pin-... » read more

Driving Toward Predictive Analytics With Dynamic Parametric Test
By Alan Hart - 06 Jul, 2021 - Comments: 0

The foundation of parametric test within semiconductor manufacturing is its usefulness in determining that wafers have been fabricated properly. Foundries use parametric test results to help verify that wafers can be delivered to a customer. For IDMs, the test determines whether the wafers can be sent on for sorting. Usually inserted into the semiconductor manufacturing flow during wafer fabric... » read more

3 Technologies That Will Challenge Test
By Ed Sperling - 08 Jun, 2021 - Comments: 0

As chips are deployed in more complex systems and with new technologies, it's not clear exactly what chipmakers and systems vendors will be testing. The standard tests for voltage, temperature and electrical throughput still will be needed, of course. But that won't be sufficient to ensure that sensor fusion, machine learning, or millimeter wave 5/6G will be functioning properly. Each of tho... » read more

Reliability Costs Becoming Harder To Track
By Ed Sperling And Susan Rambo - 08 Jun, 2021 - Comments: 0

Ensuring reliability in chips is becoming more complex and significantly more expensive, shifting left into the design cycle and right into the field. But those costs also are becoming more difficult to define and track, varying greatly from one design to the next based upon process node, package technology, market segment, and which fab or OSAT is used. As the number of options increases fo... » read more

Digging Much Deeper With Unit Retest
By Anne Meixner - 08 Jun, 2021 - Comments: 0

Keeping test costs flat in the face of product complexity continues to challenge both product and test engineers. Increased data collection at package-level test and the ability to respond to it in a never-before level of detail has prompted device makers and assembly and test houses to tighten up their retest processes. Test metrology, socket contamination, and mechanical alignment have alw... » read more

Hybrid System-Level Test For RF SiP
By Koji Miyauchi - 08 Jun, 2021 - Comments: 0

In recent years, the proliferation of the IoT has focused attention on low-power-wireless applications. IoT modules incorporating functions such as Bluetooth Low Energy (BLE) transceivers, MCUs, and power-management circuitry are becoming system-in-package (SiP) and even one-chip devices. Such devices increase the demand for a mass-production test environment that can measure them in a short ti... » read more

Monitoring Performance From Inside A Chip
By Ed Sperling - 01 Jun, 2021 - Comments: 0

Deep data, which is generated inside the chip rather than externally, is becoming more critical at each new process node and in advanced packages. Uzi Baruch, chief strategy officer at proteanTecs, talks with Semiconductor Engineering about using that data to identify potential problems before they result in failures in the field, and why it's essential to monitor these devices throughout their... » read more

Recalculating The Cost Of Test
By Ed Sperling - 11 May, 2021 - Comments: 0

The cost of test is rising. For decades, test was limited to a flat 2% of the cost of designing and manufacturing a chip. Today, no one is quite sure what that cost really is, and there doesn't seem to be any single formula for determining it. In some cases, there isn't even a sense of urgency to finding out. Several significant changes are occurring that make any formula difficult to cal... » read more

Testing Analog Circuits Becoming More Difficult
By Susan Rambo - 11 May, 2021 - Comments: 1

Foundries and packaging houses are wrestling how to control heat in the testing phase, particularly as devices continue to shrink and as thermally sensitive analog circuits are added into SoCs and advanced packages to support everything from RF to AI. The overriding problem is that heat can damage chips or devices under test. That's certainly true for digital chips developed at advanced node... » read more

Chasing Test Escapes In IC Manufacturing
By Anne Meixner - 11 May, 2021 - Comments: 0

The number of bad chips that slip through testing and end up in the field can be significantly reduced before those devices ever leave the fab, but the cost of developing the necessary tests and analyzing the data has sharply limited adoption. Determining an acceptable test escape metric for an IC is essential to improving the yield-to-quality ratio in chip manufacturing, but what exactly is... » read more

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