tag: test

Hybrid System-Level Test For RF SiP
By Koji Miyauchi - 08 Jun, 2021 - Comments: 0

In recent years, the proliferation of the IoT has focused attention on low-power-wireless applications. IoT modules incorporating functions such as Bluetooth Low Energy (BLE) transceivers, MCUs, and power-management circuitry are becoming system-in-package (SiP) and even one-chip devices. Such devices increase the demand for a mass-production test environment that can measure them in a short ti... » read more

Monitoring Performance From Inside A Chip
By Ed Sperling - 01 Jun, 2021 - Comments: 0

Deep data, which is generated inside the chip rather than externally, is becoming more critical at each new process node and in advanced packages. Uzi Baruch, chief strategy officer at proteanTecs, talks with Semiconductor Engineering about using that data to identify potential problems before they result in failures in the field, and why it's essential to monitor these devices throughout their... » read more

Recalculating The Cost Of Test
By Ed Sperling - 11 May, 2021 - Comments: 0

The cost of test is rising. For decades, test was limited to a flat 2% of the cost of designing and manufacturing a chip. Today, no one is quite sure what that cost really is, and there doesn't seem to be any single formula for determining it. In some cases, there isn't even a sense of urgency to finding out. Several significant changes are occurring that make any formula difficult to cal... » read more

Testing Analog Circuits Becoming More Difficult
By Susan Rambo - 11 May, 2021 - Comments: 1

Foundries and packaging houses are wrestling how to control heat in the testing phase, particularly as devices continue to shrink and as thermally sensitive analog circuits are added into SoCs and advanced packages to support everything from RF to AI. The overriding problem is that heat can damage chips or devices under test. That's certainly true for digital chips developed at advanced node... » read more

Chasing Test Escapes In IC Manufacturing
By Anne Meixner - 11 May, 2021 - Comments: 0

The number of bad chips that slip through testing and end up in the field can be significantly reduced before those devices ever leave the fab, but the cost of developing the necessary tests and analyzing the data has sharply limited adoption. Determining an acceptable test escape metric for an IC is essential to improving the yield-to-quality ratio in chip manufacturing, but what exactly is... » read more

A Novel Memory Test System With An Electromagnet For STT-MRAM Testing
By Advantest - 11 May, 2021 - Comments: 0

We have successfully developed, for the first time, a new memory test system for STT-MRAM at wafer-level where an electromagnet is combined with a memory test system and a 300 mm wafer prober. In the developed memory test system, an out-of-plane magnetic field up to ±800 mT can be applied on 10 x 10 mm2 in the 300 mm wafer with distribution of less than 2.5%. We demonstrated that the electroma... » read more

Merging Verification And Test
By Brian Bailey - 22 Apr, 2021 - Comments: 0

While the disciplines of functional verification and test serve different purposes, their histories were once closely intertwined. Recent safety and security monitoring requirements coupled with capabilities being embedded into devices is bringing them closer together again, but can they successfully cooperate to bring about improvements in both? Getting there may be difficult. Three phases ... » read more

Enabling The Next Step In IC Test And Monitoring
By Siemens EDA - 21 Apr, 2021 - Comments: 0

Product lifecycle management (PLM) is a well-established concept across many industries that aims to manage the entire lifecycle of a product from inception through design, realization, deployment, and field service, right through to end-of-life activities such as final disposal. More recently, these principles are being applied by the semiconductor industry because electronics continue to p... » read more

Debug And Traceability Of MCMs And Chiplets In The Manufacturing Test Process
By Guy Cortez - 16 Apr, 2021 - Comments: 0

Single die packages and products have been the norm for decades. Moreover, so has multi-chip modules (MCMs) or system in package (SiP) for quite some time. Understandably, with ASICs and SoCs becoming larger while silicon geometries continue to get smaller, there is an opportunity to combine even more functionality into a smaller form factor for the end product. Hence, new advancements in desig... » read more

MIPI D-PHY RX⁺: An Optimized Test Configuration
By Mixel - 07 Apr, 2021 - Comments: 0

With the proliferation of the mobile platform, the accelerating adoption of MIPI beyond the traditional mobile platform and into safety related applications, testability of MIPI® PHY is becoming a key requirement. While the D-PHY is the MIPI PHY with the widest adoption in the industry today, the RX+ is a D-PHY receiver configuration optimized for full-speed production testing. The presentatio... » read more

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