tag: verification IP

Harnessing Computational Storage For Faster Data Processing
By Ujjwal Negi - 14 Nov, 2024 - Comments: 0

By Ujjwal Negi and Prashant Dixit In the evolving landscape of data storage, computational storage devices (CSDs) are revolutionizing how we process and store data. By embedding processing capabilities within storage units, these devices enable in-situ data manipulation, minimizing data movement between storage and CPUs and dramatically improving performance and efficiency. This paradigm shi... » read more

Accelerating Verification Of Computational Storage Designs Using Avery NVMe Verification IP
By Siemens EDA - 14 Nov, 2024 - Comments: 0

Computational storage is an emerging paradigm that integrates processing capabilities directly within storage devices. This paper outlines how this approach addresses the limitations of traditional NVM Express (NVMe) SSDs and the performance characteristics of the newly introduced compute and subsystem local memory (SLM) namespaces. The paper also focuses on the verification framework provided ... » read more

Partial Header Encryption In Integrity And Data Encryption For PCIe
By Kunal Chhabriya - 10 Oct, 2024 - Comments: 0

Partial Header Encryption (PHE) is an additional mechanism added to Integrity and Data Encryption (IDE) in PCIe 6.0 to prevent side-channel attacks based on attacker analysis of the information included in the headers. This blog narrates PHE flow and Cadence VIP support for PHE in IDE across PCIe/CXL protocols. Background Introducing PCIe's Integrity and Data Encryption Feature is an excell... » read more

DDR5 UDIMM Evolution To Clock Buffered DIMMs (CUDIMM)
By Shyam Sharma - 26 Sep, 2024 - Comments: 0

DDR5 is the latest generation of PCDDR memory that is used in a wide range of application like data centers, Laptops and personal computers, autonomous driving systems, servers, cloud computing, and gaming are now increasingly being used for AI applications with advances in memory bandwidth and density to allow DDR5 DIMMs (Dual Inline Memory Modules) to support densities higher then 256 GB per ... » read more

The Evolution Of RISC-V Processor Verification: Open Standards And Verification IP
By Imperas - 29 Nov, 2023 - Comments: 0

The OpenHW Group’s [1] Verification task group has been a pioneer in the development of methodologies and verification collateral for RISC-V processor verification. Since 2019 the members have worked together to develop CORE-V-VERIF: a UVM environment for the verification of RISC-V processor cores. Over this period of time the CORE-V-VERIF environment has evolved as new processor verification... » read more

Extending The Benefits Of UVM To Include AMS: An Update On Accellera’s UVM-AMS Standard Development
By Tom Fitzpatrick - 04 Oct, 2022 - Comments: 0

By Tom Fitzpatrick and Peter Grove SoC teams can be divided up into design and verification groups. For digital designs, the Universal Verification Methodology (UVM), initially developed by Accellera and now standardized as IEEE 1800.2, has been the industry standard for the past decade. Since most SoC designs also have analog and mixed-signal IP blocks, it would be ideal for verification en... » read more

800G Ethernet MACsec Integration And Verification
By Cadence - 25 Aug, 2021 - Comments: 0

Ethernet is the interconnect technology of choice for a wide range of applications including (but not limited to) data centers, wireless backhaul, automotive, artificial intelligence (AI), and many other use cases. It is ubiquitous. As bandwidth requirements continue to scale to ever-dizzying heights due to the proliferation of data-intensive applications, developing, integrating, and validatin... » read more

Continuing Challenges For Open-Source Verification
By Brian Bailey - 01 Jun, 2021 - Comments: 1

Experts at the Table: This is the last part of the series of articles derived from the DVCon panel that discussed Verification in the Era of Open Source. It takes the discussion beyond what happened in the panel and utilizes some of the questions that were posed, but never presented to the panelists due to lack of time. Contributing to the discussion are Ashish Darbari, CEO of Axiomise; Serge L... » read more

Nine Effective Features Of NVMe Verification IP For PCIe-Based SSD Storage
By Siemens EDA - 10 Mar, 2021 - Comments: 0

Non-Volatile Memory Express (NVMe) is a new software interface optimized for PCIe Solid State Drives (SSD). This paper provides an overview of the NVMe specification and examines some of its key features. We will discuss its pros and cons, compare it to other conventional technologies, and point out key areas to focus on during its verification. You will learn how NVMe Questa Verification IP... » read more

Productivity Keeping Pace With Complexity
By Brian Bailey - 24 Sep, 2020 - Comments: 0

Designs have become larger and more complex and yet design time has shortened, but team sizes remain essentially flat. Does this show that productivity is keeping pace with complexity for everyone? The answer appears to be yes, at least for now, for a multitude of reasons. More design and IP reuse is using more and larger IP blocks and subsystems. In addition, the tools are improving, and mo... » read more

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