tag: advanced packaging

Solving Thermal Coupling Issues In Complex Chips
By Ann Mutschler - 10 Nov, 2022 - Comments: 0

Rising chip and packaging complexity is causing a proportionate increase in thermal couplings, which can reduce performance, shorten the lifespan of chips, and impact overall reliability of chips and systems. Thermal coupling is essentially a junction between two devices, such as a chip and a package, or a transistor and a substrate, in which heat is transferred from one to the other. If not... » read more

Balancing Power And Heat In Advanced Chip Designs
By Karen Heyman - 10 Nov, 2022 - Comments: 1

Power and heat use to be someone else's problem. That's no longer the case, and the issues are spreading as more designs migrate to more advanced process nodes and different types of advanced packaging. There are a number of reasons for this shift. To begin with, there are shrinking wire diameters, thinner dielectrics, and thinner substrates. The scaling of wires requires more energy to driv... » read more

Cost Characteristics of the 2.5D Chiplet-Based SiP System
By Technical Paper Link - 08 Nov, 2022 - Comments: 0

A technical paper titled "Cost-Aware Exploration for Chiplet-Based Architecture with Advanced Packaging Technologies" was published by researchers at UCSB, University of California, Santa Barbara. Abstract: "The chiplet-based System-in-Package~(SiP) technology enables more design flexibility via various inter-chiplet connection and heterogeneous integration. However, it is not known how to ... » read more

Heterogeneous Integration: Correcting Overlay Errors On Advanced Integrated Circuit Substrates (AICS)
By John Chang - 08 Nov, 2022 - Comments: 0

By John Chang, with Corey Shay, James Webb, and Timothy Chang For high-performance computing, artificial intelligence, and data centers, the path ahead is certain, but with it comes a change in substrate format and processing requirements. Instead of relying on the quest for the next technology node to bring about future device performance gains, manufacturers are charting a future based inc... » read more

Legacy Tools, New Tricks: Optical 3D Inspection
By Karen Heyman - 08 Nov, 2022 - Comments: 0

Stacking chips is making it far more difficult to find existing and latent defects, and to check for things like die shift, leftover particles from other processes, co-planarity of bumps, and adhesion of different materials such as dielectrics. There are several main problems: Not everything is visible from a single angle, particularly when vertical structures are used; Various struc... » read more

Chip Design Shifts As Fundamental Laws Run Out Of Steam
By Ann Mutschler - 31 Oct, 2022 - Comments: 12

Dennard scaling is gone, Amdahl's Law is reaching its limit, and Moore's Law is becoming difficult and expensive to follow, particularly as power and performance benefits diminish. And while none of that has reduced opportunities for much faster, lower-power chips, it has significantly shifted the dynamics for their design and manufacturing. Rather than just different process nodes and half ... » read more

Raising IP Integration Up A Level
By Brian Bailey - 27 Oct, 2022 - Comments: 0

An increase in the number and complexity of IP blocks, coupled with changing architectures and design concerns, are driving up the need for new tools that can enable, automate, and optimize integration in advanced chips and packages. Power, security, verification and a host of other issues are cross-cutting concerns, and they make pure hierarchical approaches difficult. Adding to future comp... » read more

Which Foundry Is In The Lead? It Depends.
By Ed Sperling - 26 Oct, 2022 - Comments: 2

The multi-billion-dollar race for foundry leadership is becoming more convoluted and complex, making it difficult to determine which company is in the lead at any time because there are so many factors that need to be weighed. This largely is a reflection of changes in the customer base at the leading edge and the push toward domain-specific designs. In the past, companies like Apple, Google... » read more

Testing 2.5D And 3D-ICs
By Ed Sperling - 25 Oct, 2022 - Comments: 0

Disaggregating SoCs allows chipmakers to cram more features and functions into a package than can fit on a reticle-sized chip. But as Vidya Neerkundar, technical marketing engineer at Siemens EDA explains, there are challenges in accessing all of the dies or chiplets in a package. The new IEEE 1838 standard addresses that, as well as what to do when 2.5D and 3D-ICs are combined together in the ... » read more

Heterogeneous Integration Co-Design Won’t Be Easy
By Tom Beckley - 13 Oct, 2022 - Comments: 0

The days of “throwing it over the wall” are over. Heterogeneous integration is ushering in a new era of silicon chip design with collaboration at its core—one that lives or dies on seamless interaction between your analog and digital IC and package design teams. Heterogeneous integration is the use of advanced packaging technologies to combine smaller, discrete chiplets into one syste... » read more

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