tag: advanced packaging

Stacking Memory On Logic, Take Two
By Ed Sperling - 19 Sep, 2019 - Comments: 1

True 3D-ICs, where a memory die is stacked on top of a logic die using through-silicon vias, appear to be gaining momentum. There are a couple reasons why this is happening, and a handful of issues that need to be considered before even seriously considering this option. None of this is easy. On a scale of 1 to 10, this ranks somewhere around 9.99, in part because the EDA tools needed to rem... » read more

Another Brick Or Two In The Chip Design Wall
By Ed Sperling - 12 Sep, 2019 - Comments: 1

Physical challenges come and go in the semiconductor world. But increasingly, they also stick around, showing up in inconvenient places at the worst time. The chip industry has confronted and solved some massive challenges over the years. There was the 1 micron lithography wall, which was supposed to be impenetrable. That was followed by the 193nm litho challenge, which cost many billions of... » read more

3D Power Delivery
By Brian Bailey - 12 Sep, 2019 - Comments: 1

Getting power into and around a chip is becoming a lot more difficult due to increasing power density, but 2.5D and 3D integration are pushing those problems to whole new levels. The problems may even be worse with new packaging approaches, such as chiplets, because they constrain how problems can be analyzed and solved. Add to that list issues around new fabrication technologies and an emph... » read more

Test On New Technology’s Frontiers
By SE Staff - 10 Sep, 2019 - Comments: 2

Semiconductor testing is getting more complicated, more time-consuming, and increasingly it requires new approaches that have not been fully proven because the technologies they are addressing are so new. Several significant shifts are underway that make achieving full test coverage much more difficult and confidence in the outcome less certain. Among them: Devices are more connected an... » read more

Nvidia’s Top Technologists Discuss The Future Of GPUs
By SE Staff - 10 Sep, 2019 - Comments: 0

Semiconductor Engineering sat down to discuss the role of the GPU in artificial intelligence, autonomous and assisted driving, advanced packaging and heterogeneous architectures with Bill Dally, Nvidia’s chief scientist, and Jonah Alben, senior vice president of Nvidia’s GPU engineering, at IEEE’s Hot Chips 2019 conference. What follows are excerpts of that conversation. SE: There are ... » read more

Advanced Packaging Options Increase
By Ed Sperling - 19 Aug, 2019 - Comments: 0

Designing, integrating and assembling heterogeneous packages from blocks developed at any process node or cost point is proving to be far more difficult than expected, particularly where high performance is one of the main criteria. At least part of the problem is there is a spectrum of choices, which makes it hard to achieve economies of scale. Even where there is momentum for a particular ... » read more

Why Scaling Must Continue
By Ed Sperling - 15 Aug, 2019 - Comments: 3

The entire semiconductor industry has come to the realization that the economics of scaling logic are gone. By any metric—price per transistor, price per watt, price per unit area of silicon—the economics are no longer in the plus column. So why continue? The answer is more complicated than it first appears. This isn't just about inertia and continuing to miniaturize what was proven in t... » read more

Speed Returns As The Key Metric
By Ed Sperling - 08 Aug, 2019 - Comments: 0

For the foreseeable future, it's all about performance. For the past decade or so, power and battery life have been the defining characteristics of chip design. Performance was second to those. This was particularly important in smart phones and wearable devices, where time between charges was a key selling point. In fact, power-hungry processors killed the first round of smart watches. But ... » read more

Using Better Data To Shorten Test Time
By Ed Sperling - 06 Aug, 2019 - Comments: 1

The combination of machine learning plus more sensors embedded into IC manufacturing equipment is creating new possibilities for more targeted testing and faster throughput for fabs and OSATs. The goal is to improve quality and reduce the cost of manufacturing complex chips, where time spent in manufacturing is ballooning at the most advanced nodes. As the number of transistors on a die incr... » read more

Cloudy Outlook Seen For IC Biz
By Mark LaPedus - 29 Jul, 2019 - Comments: 0

After a slowdown in the first half of 2019, chipmakers and equipment vendors face a cloudy outlook for the second half of this year, with a possible recovery in 2020. Generally, the semiconductor industry began to see a slowdown starting in mid- to late-2018, which extended into the first half of 2019. During the first half of this year, memory and non-memory vendors were negatively impacted... » read more

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