tag: advanced packaging

Scaling Sideways
By Ed Sperling - 19 Jul, 2018 - Comments: 0

The next steps in semiconductor technology don't follow the same vectors. While 3nm chips are likely to roll out at some point in the future, it's not clear what the business case will be for developing them. What's clear is the number of companies developing chips at that node will shrink to a handful (or less), because they're going to be far too expensive to design, verify and manufacture... » read more

New Roadmap For Electronics
By Ed Sperling - 19 Jul, 2018 - Comments: 0

Tech Talk: Melissa Grupen-Shemansky, CTO for SEMI’s FlexTech Group and Advanced Packaging program, looks at what’s changing now that Moore’s Law is slowing, and how packaging is changing as the traditional physical boundaries of electronics begin breaking down. https://youtu.be/UpH1m8Oru90 » read more

Fostering Thermal Design Innovation Using Chip-Package-System Analysis Techniques
By Ansys - 16 Jul, 2018 - Comments: 0

As devices continue to become smaller and more portable Moore’s Law continues to increase the number of transistors that fit within a chip albeit many predict an end to this in the near future. However new interconnect technologies that use Through-Silicon-Vias (TSVs) can place ICs next to each other using 2.5D Interposers or stack chips in 3D resulting in even greater system scaling. This co... » read more

Tech Talk: Connected Intelligence
By Ed Sperling - 21 Jun, 2018 - Comments: 0

Gary Patton, CTO at GlobalFoundries, talks about computing at the edge, the slowdown in scaling, and why new materials and packaging approaches will be essential in the future. https://youtu.be/Zbz0R_yFFrQ » read more

Complexity, Reliability And Cost
By Ed Sperling - 14 Jun, 2018 - Comments: 0

Peter Schneider, director of Fraunhofer's Engineering of Adaptive Systems Division, sat down with Semiconductor Engineering to talk about future challenges in complexity, time to market and reliability issues, advanced packaging architectures, and the impact of billions of connected devices. What follows are excerpts of that discussion. SE: What is the biggest challenge you see in the semico... » read more

Advanced Packaging Confusion
By Ed Sperling - 13 Jun, 2018 - Comments: 2

Advanced packaging is exploding in all directions. There are more chipmakers utilizing different packaging options, more options for the packages themselves, and a confusing array of descriptions and names being used for all of these. Several years ago, there were basically two options on the table, 3D-ICs and 2.5D. But as chipmakers began understanding the difficulty, cost and reduced benef... » read more

Sacrificial Laser Release Materials For RDL-First Fan-Out Packaging
By Brewer Science - 11 Jun, 2018 - Comments: 0

The semiconductor industry is in a new age where device scaling will not continue to provide the cost reductions or performance improvements at a similar rate to past years when Moore’s law was the guiding principle for IC scaling. The cost of scaling below 7 nm nodes is rising substantially and requires significant investment in capital equipment and R&D spending for next-generation lithogra... » read more

Extending The IC Roadmap
By Mark LaPedus - 11 Jun, 2018 - Comments: 0

An Steegen, executive vice president of semiconductor technology and systems at Imec, sat down with Semiconductor Engineering to discuss IC scaling and chip packaging. Imec is working on next-generation transistors, but it is also developing several new technologies for IC packaging, such as a proprietary silicon bridge, a cooling technology and packaging modules. What follows are excerpts of t... » read more

Analog Migration Equals Redesign
By Ann Mutschler - 24 May, 2018 - Comments: 1

Analog design has never been easy. Engineers can spend their entire careers focused just on phase-locked loops (PLLs), because to get them right the functionality of circuits need to be understood in depth, including how they respond across different process corners and different manufacturing processes. In the finFET era, those challenges have only intensified for analog circuits. Reuse, fo... » read more

Early Chip-Package-System Thermal Analysis
By Annapoorna Krishnaswamy - 10 May, 2018 - Comments: 0

Next-generation automotive, HPC and networking applications are pushing the requirements of thermal integrity and reliability, as they need to operate in extreme conditions for extended periods of time. FinFET designs have high dynamic power density, and power directly impacts the thermal signature of the chip. Thermal degradation typically occurs over an extended period of chip operation. ... » read more

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