tag: advanced packaging

Tech Talk: HBM vs. GDDR6
By Ed Sperling - 10 May, 2018 - Comments: 0

Frank Ferro, senior director of product management at Rambus, talks about memory bottlenecks and why both GDDR6 and high-bandwidth memory are gaining steam and for which markets. https://youtu.be/CPqdZZooS2g     Related Video GDDR6 – HBM2 Tradeoffs (2019) What type of DRAM works best where. » read more

Tech Talk: Shrink Vs. Package
By Ed Sperling - 10 May, 2018 - Comments: 0

Andy Heinig, group manager for system integration at Fraunhofer EAS, talks about the tradeoffs between planar design and advanced packaging, including different types of interposers, chiplets and thermal issues. https://youtu.be/1BDqgCujJno » read more

The Case For Chiplets
By Ed Sperling - 07 May, 2018 - Comments: 4

Discussion about chiplets is growing as the cost of developing chips at 10/7nm and beyond passes well beyond the capabilities of many chipmakers. Estimates for developing 5nm chips (the equivalent 3nm for TSMC and Samsung) are well into the hundreds of millions of dollars just for the NRE costs alone. Masks costs will be in the double-digit millions of dollars even with EUV. And that's assum... » read more

MIS Packaging Takes Off
By Mark LaPedus - 07 May, 2018 - Comments: 0

Momentum is building for IC packages based on an emerging technology called molded interconnect substrate (MIS). ASE, Carsem, JCET/STATS ChipPAC, Unisem and others are developing IC packages based on MIS substrate technology, which is ramping up in the analog, power IC and even the cryptocurrency markets. MIS starts with a specialized substrate material for select IC packages. The MIS sub... » read more

Package Designers Need Assembly-Level LVS For HDAP Verification
By Mentor, a Siemens Business - 07 May, 2018 - Comments: 0

While advanced IC packaging is a fast-growing market, comprehensive package verification still has a ways to go. Unique package connectivity issues, such as missing or misplaced interposer/package bumps/pads, pin naming and text labeling issues, and the like, require new and enhanced LVS-like verification techniques that can move across the entire package to ensure proper connectivity and perfo... » read more

More Nodes, New Problems
By Ann Mutschler - 26 Apr, 2018 - Comments: 0

The rollout of leading-edge process nodes is accelerating rather than slowing down, defying predictions that device scaling would begin to subside due to rising costs and the increased difficulty of developing chips at those nodes. Costs are indeed rising. So are the number of design rules, which reflect skyrocketing complexity stemming from multiple patterning, more devices on a chip, and m... » read more

Multi-Die Packaging And Thermal Superposition Modeling
By eSilicon - 25 Apr, 2018 - Comments: 0

Packaging density, electrical performance and cost are the primary factors driving electronic package architectures for high-performance server markets. Considerations such as thermal performance and mechanical reliability are equally important but tend to be addressed later in the design cycle. Presented in this paper is a historical view of the packaging trends leading to the current multi-di... » read more

Tech Talk: Analog Simplified
By Ed Sperling - 16 Apr, 2018 - Comments: 0

Benjamin Prautsch, Fraunhofer EAS' group manager for advanced mixed-signal automation, talks about how to simplify and speed up analog IP development, its role in IoT and IIoT/Industry 4.0, and why this is becoming so important for advanced packaging and advanced process nodes. https://youtu.be/6ISL1A7Wy_I » read more

Architecture, Materials And Software
By Ed Sperling - 12 Apr, 2018 - Comments: 0

AI, machine learning and autonomous vehicles will require massive improvements in performance, at the same power consumption level (or better), over today's chips. But it's obvious that the usual approach of shrinking features to improve power/performance isn't going to be sufficient. Scaling will certainly help, particularly on the logic side. More transistors are needed to process a huge i... » read more

The Race To Mass Customization
By Ed Sperling - 09 Apr, 2018 - Comments: 0

The number of advanced packaging options continues to rise. The choices now include different materials for interposers, at least a half-dozen fan-outs, not to mention hybrid fan-out/3D stacking, system-in-package, flip-chip and die-to-die bridges. There are several reasons for all of this activity. First, advanced packaging offers big improvements in performance and power that cannot be ac... » read more

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