tag: AI

RaPiD: AI Accelerator for Ultra-low Precision Training and Inference
By Technical Paper Link - 02 Jul, 2021 - Comments: 0

Abstract—"The growing prevalence and computational demands of Artificial Intelligence (AI) workloads has led to widespread use of hardware accelerators in their execution. Scaling the performance of AI accelerators across generations is pivotal to their success in commercial deployments. The intrinsic error-resilient nature of AI workloads present a unique opportunity for performance/energy i... » read more

Challenges Of Edge AI Inference
By Vinay Mehta - 01 Jul, 2021 - Comments: 0

Bringing convolutional neural networks (CNNs) to your industry—whether it be medical imaging, robotics, or some other vision application entirely—has the potential to enable new functionalities and reduce the compute requirements for existing workloads. This is because a single CNN can replace more computationally expensive image processing, denoising, and object detection algorithms. Howev... » read more

Challenges In Developing A New Inferencing Chip
By Ed Sperling - 01 Jul, 2021 - Comments: 0

Cheng Wang, co-founder and senior vice president of software and engineering at Flex Logix, sat down with Semiconductor Engineering to explain the process of bringing an inferencing accelerator chip to market, from bring-up, programming and partitioning to tradeoffs involving speed and customization.   SE: Edge inferencing chips are just starting to come to market. What challenges di... » read more

ACAP At The Edge With The Versal AI Edge Series
By Xilinx - 30 Jun, 2021 - Comments: 0

This white paper introduces the AI Edge series to the Versal ACAP portfolio, a domain-specific architecture (DSA) that meets the strenuous demands of systems implemented in the 7nm silicon process. This series is optimized to meet the performance-per-watt requirements of edge nodes at or near the analog-digital boundary. Here, immediate response to the physical world is highly valued, and in ma... » read more

Debug: The Schedule Killer
By Brian Bailey - 30 Jun, 2021 - Comments: 0

Debug often has been labeled the curse of management and schedules. It is considered unpredictable and often can happen close to the end of the development cycle, or even after – leading to frantic attempts at work-arounds. And the problem is growing. "Historically, about 40% of time is spent in debug, and that aspect is becoming more complex," says Vijay Chobisa, director of product manag... » read more

Manufacturing Bits: June 29
By Mark LaPedus - 29 Jun, 2021 - Comments: 0

Speeding up ALD with AI The U.S. Department of Energy’s (DOE) Argonne National Laboratory has developed various ways to make atomic layer deposition (ALD) more efficient by using artificial intelligence (AI). ALD is a deposition technique that deposits materials one layer at a time on chips. For years, ALD has been used for the production of DRAMs, logic devices and other products. In ... » read more

CEO Outlook: More Data, More Integration, Same Deadlines
By Ed Sperling - 24 Jun, 2021 - Comments: 1

Experts at the Table: Semiconductor Engineering sat down to discuss the future of chip design and EDA tools with Lip-Bu Tan, CEO of Cadence; Simon Segars, CEO of Arm; Joseph Sawicki, executive vice president of Siemens IC EDA; John Kibarian, CEO of PDF Solutions; Prakash Narain, president and CEO of Real Intent; Dean Drako, president and CEO of IC Manage; and Babak Taheri, CEO of Silvaco. What ... » read more

Bumps Vs. Hybrid Bonding For Advanced Packaging
By Mark LaPedus - 23 Jun, 2021 - Comments: 3

Advanced packaging continues to gain steam, but now customers must decide whether to design their next high-end packages using existing interconnect schemes or move to a next-generation, higher-density technology called copper hybrid bonding. The decision is far from simple, and in some cases both technologies may be used. Each technology adds new capabilities in next-generation advanced pac... » read more

An Advanced Infrastructure To Enable Secure, Cloud-Aware Design And Processed Data EDA Tool Interoperability
By Si2 - 22 Jun, 2021 - Comments: 0

By Rajeev Jain, Kerim Kalafala, and Ramond Rodriguez Significant technology disruptions are on the horizon that will provide massive efficiency gains for EDA tool suppliers and semiconductor companies alike. These disruptions include the application of artificial intelligence and machine learning to enhance supplier tools and optimize user design flows and methodologies, and the ensuing migr... » read more

Shifting Toward Data-Driven Chip Architectures
By Ed Sperling and Ann Mutschler - 16 Jun, 2021 - Comments: 0

An explosion in data is forcing chipmakers to rethink where to process data, which are the best types of processors and memories for different types of data, and how to structure, partition and prioritize the movement of raw and processed data. New chips from systems companies such as Google, Facebook, Alibaba, and IBM all incorporate this approach. So do those developed by vendors like Appl... » read more

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