Wafer Level Void-Free Molded Underfill For High-Density Fan-out Packages


In this study, experiments and mold flow simulation results are presented for a void-free wafer level molded underfill (WLMUF) process with High-Density Fan-Out (HDFO) test vehicles using a wafer-level compression molding process. The redistribution layer (RDL)-first technology was applied with 3 layers of a fine-pitch RDL structure. The test samples comprised 11.5 x 12.5-mm2 die with tall copp... » read more

Week In Review: Manufacturing, Test


Acquisitions & Investments California-based MaxLinear plans to acquire Taiwan-based Silicon Motion (SMI), in a cash and stock deal valued at about $3.8 billion. Silicon Motion’s NAND flash controller technology for solid state storage devices, will extend MaxLinear’s RF, analog, and mixed signal portfolio. ISMC will invest about $3 billion in a semiconductor plant in India’s south... » read more

Paving The Way To Chiplets


The packaging industry is putting pieces in place to broaden the adoption of chiplets beyond just a few chip vendors, setting the stage for next-generation 3D chip designs and packages. New chiplet standards, and a cost analysis tool for determining the feasibility of a given chiplet-based design, are two new and important pieces. Along with other efforts, the goal is to propel the chiplet m... » read more

Vehicle Electrification Driving Supply Chain Evolution


Dr. Ajay Sattu, Director, Automotive Product Marketing, Amkor Technology, Inc. If the recently concluded CES 2022 is any indication, the automotive industry is yet again in the cross hairs of both consumers and industry experts alike. Whether it’s the new electric vehicle (EV) model introductions, color changing technologies, or concept cars, automotive companies are slowly transforming th... » read more

Finding And Applying Domain Expertise In IC Analytics


Behind PowerPoint slides depicting the data inputs and outputs of a data analytics platform belies the complexity, effort, and expertise that improve fab yield. With the tsunami of data collected for semiconductor devices, fabs need engineers with domain expertise to effectively manage the data and to correctly learn from the data. Naively analyzing a data set can lead to an uninteresting an... » read more

Week In Review: Manufacturing, Test


Chipmakers, OEMs Intel continues to build more fabs. First, the company announced fabs in Arizona and then Ohio. Now, Intel plans to invest up to €80 billion in the European Union over the next decade. As part of the effort, Intel plans to build two semiconductor fabs in Magdeburg, Germany. Construction is expected to begin in the first half of 2023 and production planned to come online in 2... » read more

Chiplets Enter The Supercomputer Race


Several entities from various nations are racing each other to deliver and deploy chiplet-based exascale supercomputers, a new class of systems that are 1,000x faster than today’s supercomputers. The latest exascale supercomputer CPU and GPU designs mix and match complex dies in advanced packages, adding a new level of flexibility and customization for supercomputers. For years, various na... » read more

Week In Review: Manufacturing, Test


Chipmakers Intel has announced a definitive agreement to acquire Tower, a specialty foundry vendor, for approximately $5.4 billion. With the acquisition of Tower, Intel expands its efforts in the foundry business, and put its rivals on notice. With Tower, Intel gains access to mature processes as well as specialty technologies, such as analog, CMOS image sensor, MEMS, power management and RF. ... » read more

Technology Advances, Shortages Seen For Wire Bonders


A surge in demand for IC packages is causing long lead times for wire bonders, which are used to assemble three-fourths of the world’s packages. The wire bonder market doubled last year, alongside advanced packaging’s rise. Wirebonding is an older technology that typically flies under the radar. Still, packaging houses have multitudes of these key tools that help assemble many — but no... » read more

Thermal Management Implications For Heterogeneous Integrated Packaging


As the semiconductor industry reaches lower process nodes, silicon designers struggle to have Moore's Law produce the results achieved in earlier generations. Increasing the die size in a monolithic system on chip (SoC) designs is no longer economically viable. The breakdown of monolithic SoCs into specialized chips, referred to as chiplets, presents significant benefits in terms of cost, yield... » read more

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