tag: Atrenta

3D ICs: No Simple Answers
By Ed Sperling - 31 Mar, 2011 - Comments: 0

By Pallab Chatterjee Just how ready is the semiconductor industry for stacked die? That was the subject of a recent panel discussion involving ARM, Atrenta, Xilinx, Samsung and Mentor Graphics. The reasoning behind 3D stacking is becoming clearer at each node. I/O count and delay times are forcing different configurations, but the time frames for these changes and the gating constraints are... » read more

Speeding Tickets
By Frank Ferro - 31 Mar, 2011 - Comments: 0

By Frank Ferro Speed sells. Bells and whistles are always intriguing and fun to have, but the driver for new products is usually speed. We want to move our phones to the 4G network for faster download speeds, or replace our 802.11g home router with the new 802.11n, we want a PC with a dual-core processor to replace the single-core processor, and the list goes on. Clearly speed is an easy way t... » read more

Good Times, Good People
By Atrenta - 31 Mar, 2011 - Comments: 0

I lost a long-time friend this past week. He was a member of the EDA community and so I will dedicate this blog to a discussion of the late Dr. Aaron Ashkinazy—the person, his contributions and the process for his work. The person. Aaron had a lot of friends. We’ve all been reminiscing about him this past week and some consistent comments arise. He was one of the most intelligent and kin... » read more

Experts At The Table: 3D Stacking
By Ed Sperling - 14 Mar, 2011 - Comments: 0

By Ed Sperling Semiconductor Manufacturing and Design sat down with Riko Radojcic, director of engineering at Qualcomm; Drew Wingard, CTO at Sonics; Michael White, senior product marketing manager for Calibre physical verification at Mentor Graphics; Jim Hogan, a Silicon Valley venture capitalist; Prasad Subramaniam, vice president of design technology at eSilicon; and Mike Gianfagna, vice pr... » read more

Experts At The Table: 3D Stacking
By Ed Sperling - 25 Feb, 2011 - Comments: 0

By Ed Sperling Semiconductor Manufacturing and Design sat down with Riko Radojcic, director of engineering at Qualcomm; Drew Wingard, CTO at Sonics; Michael White, senior product marketing manager for Calibre physical verification at Mentor Graphics; Jim Hogan, a Silicon Valley venture capitalist; Prasad Subramaniam, vice president of design technology at eSilicon; and Mike Gianfagna, vice pr... » read more

Experts At The Table: Concurrent Design
By Ed Sperling - 25 Feb, 2011 - Comments: 0

Low-Power Engineering sat down with Marco Brambilla, ASIC design manager at STMicroelectronics; Charlie Janac, president and CEO of Arteris; Mike Gianfagna, vice president of marketing at Atrenta, and Javier DeLaCruz, director of semiconductor packaging at eSilicon. What follows are excerpts of that discussion. LPE: Is concurrent design strategic—meaning is it done at the architectural lev... » read more

Memory, Bandwidth And SoC Performance
By Ed Sperling - 24 Feb, 2011 - Comments: 0

By Ann Steffora Mutschler High-end SoC architectures today can contain dozens of processing engines—multiple cores from MIPS and ARM, DSPs from Tensilica and CEVA, and even graphics processors. But with so many cores there also is a need for enormous amounts of memory, and that has been creating some unexpected design problems, In many cases so much memory is required for an SoC that some... » read more

The Growing Importance Of Subsystems
By Ed Sperling - 24 Feb, 2011 - Comments: 0

By Ed Sperling A growing reliance on third-party IP is beginning to expand well beyond just IP blocks and into full subsystems, opening significant growth opportunities for companies competing in this market as well as enormous business and technical challenges. The IP market is ripe for this kind of convergence. Complexity at advanced process nodes coupled with time-to-market demands has e... » read more

Chip Failure? Don’t Worry About It!
By Ron Craig - 24 Feb, 2011 - Comments: 0

By Ron Craig Here in the United States it’s tax time again. Along with every other loyal taxpayer, I’ve been working on identifying every conceivable deduction I can think of to minimize my overall tax burden. I’m not an expert on tax law, but as far as I can tell I still can’t take advantage of the non-tax deductible dependents we like to call ‘the cats.’ Our own demanding hous... » read more

Experts At The Table: Concurrent Design
By Ed Sperling - 18 Feb, 2011 - Comments: 0

Low-Power Engineering sat down with Marco Brambilla, ASIC design manager at STMicroelectronics; Charlie Janac, president and CEO of Arteris; Mike Gianfagna, vice president of marketing at Atrenta, and Javier DeLaCruz, director of semiconductor packaging at eSilicon. What follows are excerpts of that discussion. LPE: Is there cross-training going on to allow for concurrent design? Brambilla... » read more

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