tag: Atrenta

SoC Physical Closure Begins At RTL
By Various Writers - 16 Jun, 2010 - Comments: 0

Any survey of chip design teams consistently points to two problem areas impacting quality and schedule of today's SoCs. Those areas are: a) completeness of verification, and b) physical design closure for area, timing and power for complex IP's and SoC's. With the advent of deep sub-micron technology, these problem areas have become exacerbated. In this White Paper, we take a closer look at th... » read more

Experts At The Table: Nice To Have Vs. Need To Have
By Ed Sperling - 10 Jun, 2010 - Comments: 0

Low-Power Engineering sat down to discuss what’s essential and what isn’t in EDA with Brani Buric, executive vice president at Virage Logic; Kalar Rajendiran, senior director of marketing at eSilicon; Mike Gianfagna, vice president of marketing at Atrenta, and Oz Levia, vice president of marketing and business development at Springsoft. What follows are excerpts of that conversation. LPE... » read more

Timing Closure And Denial
By Ron Craig - 10 Jun, 2010 - Comments: 0

By Ron Craig I live in a reasonably remote area—defined as more than 10 miles from the nearest Starbucks. Given that I spend a fair amount of time driving, I’m conscious of things like safety and mileage. One thing that has a big impact on both is the health of my tires, and after having a recent replacement set installed I noticed that my ‘local’ tire shop offered things like regula... » read more

Constraints Management
By Various Writers - 27 May, 2010 - Comments: 0

As the complexity of designs has scaled, the need to provide accurate physical constraints like timing, area, power and port locations has become increasingly important. Of these, timing constraints are the most difficult to provide since they depend on many external factors like floor planning, routing and integration with other blocks. Properly created timing constraints not only reduce the t... » read more

Timing Bomb
By Ed Sperling - 22 Apr, 2010 - Comments: 0

By Ed Sperling Timing closure, a basic operation in chip design and development, is becoming anything but basic at advanced process nodes. Systematic variability that was at least predictable at 90nm has become random at 45nm. Tools that worked fine with two corner cases now have to deal with hundreds. And as more functions make their way onto a single die, often with multiple modes of oper... » read more

Do Your Chip A Favor: Manage The Constraints
By Various Writers - 22 Apr, 2010 - Comments: 0

A design goes through several transformations in a typical register transfer level (RTL) to layout flow, and a variety of verification techniques are employed (simulation, equivalence checking, etc.) to ensure that its intent has not changed. It’s normal for timing constraints to be created and refined in parallel with the RTL and netlist throughout the design cycle, but these constraints t... » read more

Mind The Gap
By Ed Sperling - 25 Feb, 2010 - Comments: 0

By Ed Sperling Throughout system-level design there are gaps. High-level modeling doesn’t connect directly to RTL code. Synthesis and high-level synthesis remain worlds apart. There are even gaps in the expertise, from the people who handcraft RTL to those who take it for granted. Some of these gaps will get closed over time. Others will never be closed. In same cases it doesn’t matter.... » read more

GuideWare
By Various Writers - 25 Feb, 2010 - Comments: 0

Advances in silicon technology have enabled unprecedented levels of integration in today’s SoC designs. These designs are developed through integration of various sub-systems. After the architecture and top-level micro-architecture are reasonably complete, the task of developing and integrating sub-systems begins. These sub-systems may be developed ground-up with brand new sub-system RTL. A... » read more

Remaking The Design Landscape
By Ed Sperling - 28 Jan, 2010 - Comments: 0

By Ed Sperling Every now and then a new trend comes along in the semiconductor design world, often because an old tool doesn’t work well anymore or because a new one is achieving critical mass. Lithography moved to immersion when the wavelength couldn’t be refracted far enough anymore. Designers at the advanced end of Moore’s Law began using tools like high-level synthesis and Transa... » read more

SpyGlass-CDC: Combining Structural And Functional Verification Techniques
By Various Writers - 28 Jan, 2010 - Comments: 0

Multiple, independent clocks are quintessential in SoCs and other complex ASICs today. In some cases, such as in large communications processors, clock domains may number in the hundreds. Clock domain crossings pose a growing challenge to chip designers, and constitute a major source of design errors--errors that can easily slip past conventional verification tools and make their way into sil... » read more

← Older posts Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2024 SMG   |  Terms of Service  |  Privacy Policy