Test Challenges Mount As Demands For Reliability Increase


An emphasis of improving semiconductor quality is beginning to spread well beyond just data centers and automotive applications, where ICs play a role in mission- and safety-critical applications. But this focus on improved reliability is ratcheting up pressure throughout the test community, from lab to fab and into the field, in products where transistor density continues to grow — and wh... » read more

The 5G mmWave Commercialization Effort Is Underway


By David Vondran and Rodrigo Carrillo-Ramirez 5G broadband cellular technology entered its first major rollout phase in 2019. In recent years, 5G adoption has been very visible among the consumer electronics industry, with 5G capabilities now being a key selling point for mid-tier to high-end mobile devices. Behind the scenes, however, there have been a number of developments designed to ... » read more

Preparing For Test Early In The Design Flow


Until very recently, semiconductor design, verification, and test were separate domains. Those domains have since begun to merge, driven by rising demand for reliability, shorter market windows, and increasingly complex chip architectures. In the past, products were designed from a functional perspective, and designers were not concerned about what the physical implementation of the product ... » read more

High-Quality Test And Embedded Analytics Are Vital For Secure SoCs


Applications like as smart cards and devices used in the defense industry require security to ensure that sensitive data is inaccessible to outside agents. This used to be a niche requirement met through custom solutions. However, now that automotive and cyber-physical systems are proliferating, the requirements around secure test and monitoring are becoming mainstream. The current best strateg... » read more

More Errors, More Correction in Memories


As memory bit cells of any type become smaller, bit error rates increase due to lower margins and process variation. This can be dealt with using error correction to account for and correct bit errors, but as more sophisticated error-correction codes (ECC) are used, it requires more silicon area, which in turn drives up the cost. Given this trend, the looming question is whether the cost of ... » read more

Don’t Let X Be A Problem For Logic BIST


By Rahul Singhal and Giri Podichetty A failure in the operation of integrated circuits (ICs) or chips deployed in safety-critical applications such as automotive, medical, and aerospace could have catastrophic consequences. These failures could stem from defects in the chip that escaped manufacturing tests or from transient faults that can occur during system operation due to factors such as... » read more

MBIST-supported Trim Adjustment to Compensate Thermal Behavior of MRAM


Abstract: "Spin Transfer Torque Magnetic Random Access Memory (STT-MRAM) is one of the most promising candidates to replace conventional embedded memory such as Static RAM and Dynamic RAM. However, due to the small on/off ratio of MRAM cells, process variations may reduce the operating margin of a chip. Reference trimming was suggested as one of the ways to reduce variation impact to the chi... » read more

Chip Monitoring And Test Collaborate


As on-chip monitoring becomes more prevalent in complex advanced-node ICs, it’s easy to question whether or not it conflicts with conventional silicon testing. It might even supplant such testing in the future. Or alternatively, they could interact, with each supporting the other. “On-chip monitors provide fine-grained observability into effects and issues that are otherwise difficult or... » read more

Tessent LogicBIST With Observation Scan Technology


Meeting the ISO 26262 requirements for high quality and long-term reliability mans implementing on-chip safety mechanisms with high defect coverage of IC logic. This paper describes Observation Scan Technology, a new new logic built-in-self-test (BIST) technology that improves logic BIST test quality and reduces in-system test time. Empirical results demonstrate 90% test coverage with up to 10X... » read more

Scramble For The White Space


Chipmakers are pushing to utilize more of the unused portion of a design for different functions, reducing margin in the rest of the chip to more clearly define that white space. White space typically is used to relieve back-end routing congestion before all of the silicon area is used up. But a significant amount of space still remain unused. That provides an opportunity for inserting monit... » read more

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