tag: bonding

Surface-Activated ALD For Room-Temperature Bonding of Al2O3
By Technical Paper Link - 03 Apr, 2023 - Comments: 0

A new technical paper titled "Room-temperature bonding of Al2O3 thin films deposited using atomic layer deposition" was published by researchers at Kyushu University. Abstract "In this study, room-temperature wafer bonding of Al2O3 thin films on Si thermal oxide wafers, which were deposited using atomic layer deposition (ALD), was realized using the surface-activated bonding (SAB) metho... » read more

Managing Thermal-Induced Stress In Chips
By Karen Heyman - 16 Feb, 2023 - Comments: 0

At advanced nodes and in the most advanced packages, physics is no one's friend. Escalating density, smaller features, and thinner dies make it more difficult to dissipate heat, and they increase mechanical stress. On the flip side, thinner dielectrics and tighter spaces make it more difficult to insulate and protect against that heat, and in conjunction with those smaller features and higher d... » read more

Unknowns And Challenges In Advanced Packaging
By Ed Sperling - 19 Jan, 2023 - Comments: 0

Dick Otte, CEO of Promex Industries, sat down with Semiconductor Engineering to talk about unknowns in material properties, the impact on bonding, and why environmental factors are so important in complex heterogeneous packages. What follows are excerpts of that conversation. SE: Companies have been designing heterogeneous chips to take advantage of specific applications or use cases, but th... » read more

New Method to Measure, At The Wafer Scale, Direct Bonding Energies (CEA-LETI)
By Technical Paper Link - 12 Dec, 2022 - Comments: 0

A new technical paper titled "Double cantilever beam bonding energy measurement using confocal IR microscopy" was published by researchers at Univ. Grenoble Alpes, CEA-LETI and SOITEC, Parc Technologique des Fontaines. "A new technique is assessed in order to measure, at the wafer scale, direct bonding energies. It is derived from the standard Double Cantilever Beam (DCB) method and uses int... » read more

Hot Trends In Semiconductor Thermal Management
By Karen Heyman - 17 Nov, 2022 - Comments: 1

Increasing thermal challenges, as the industry moves into 3D packaging and continues to scale digital logic, are pushing the limits of R&D. The basic physics of having too much heat trapped in too small a space is leading to tangible problems, like consumer products that are too hot to hold. Far worse, however, is the loss of power and reliability, as overheated DRAM has to continually r... » read more

Big Changes In Materials And Processes For IC Manufacturing
By Ed Sperling And Laura Peters - 21 Apr, 2022 - Comments: 3

Rama Puligadda, CTO at Brewer Science, sat down with Semiconductor Engineering to talk about a broad set of changes in semiconductor manufacturing, packaging, and materials, and how that will affect reliability, processes, and equipment across the supply chain. SE: What role do sacrificial materials play in semiconductor manufacturing, and how is that changing at new process nodes? Puliga... » read more

Bumps Vs. Hybrid Bonding For Advanced Packaging
By Mark LaPedus - 23 Jun, 2021 - Comments: 3

Advanced packaging continues to gain steam, but now customers must decide whether to design their next high-end packages using existing interconnect schemes or move to a next-generation, higher-density technology called copper hybrid bonding. The decision is far from simple, and in some cases both technologies may be used. Each technology adds new capabilities in next-generation advanced pac... » read more

Brighter Future For Photonics
By Brian Bailey - 13 Feb, 2020 - Comments: 3

Photons increasingly are taking over where electrons are failing in communications, but mixing the two never has been easy. There always have been two potential implementation paths — building each on its own substrate and then stacking them, or building them on a single substrate. The tradeoff between the two solutions is more complex than it may initially appear, and ongoing improvements... » read more

Investigation and Methods Using Various Release and Thermoplastic Bonding Materials to Reduce Die Shift and Wafer Warpage for eWLB Chip-First Processes
By Brewer Science - 14 Aug, 2019 - Comments: 0

Today's fan-out wafer-level packaging (FOWLP) processes use organic substrates composed of epoxy mold compound (EMC) created using a thermal compression process. EMC wafers are a cost-effective way to achieve lower profile packages without using an inorganic substrate to produce chip packages that are thinner and faster without the need for interposers or through-silicon-vias (TSVs). One approa... » read more

Partitioning In 3D
By Katherine Derbyshire - 23 May, 2019 - Comments: 2

The best way to improve transistor density isn't necessarily to cram more of them onto a single die. Moore’s Law in its original form stated that device density doubles about every two years while cost remains constant. It relied on the observation that the cost of a processed silicon wafer remained constant regardless of the number of devices printed on it, which in turn depended on litho... » read more

← Older posts Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2026 SMG   |  Terms of Service  |  Privacy Policy