tag: Cadence

Blog Review: Sept. 5
By Jesse Allen - 05 Sep, 2018 - Comments: 0

Synopsys' Taylor Armerding looks at a case of exploding costs – up to $17 million – when the city of Atlanta, Georgia fell victim to the SamSam ransomware, plus the lessons other cities can take to improve their security. Cadence's Paul McLellan traces how a landmark moment in object recognition, the ImageNet database, has spurred increasingly better object recognition algorithms for alm... » read more

Week In Review: Design, Low Power
By Jesse Allen - 31 Aug, 2018 - Comments: 0

Synopsys unveiled a new formal app, Regression Mode Accelerator, which uses machine learning algorithms to speed up formal property verification, as well as better convergence of formal proofs for subsequent runs. According to Synopsys, the app also allows for significant saving of compute resources in nightly regressions. Hitachi used OneSpin Solutions' 360 EC product family to verify vCOSS... » read more

Variation In Low-Power FinFET Designs
By Ann Mutschler - 30 Aug, 2018 - Comments: 1

One of the biggest advantages of moving to the a leading edge process node is ultra-low voltage operation, where devices can achieve better performance using less power. But the latest generation process nodes also introduce a number of new challenges due to increased variation that can affect everything from signal integrity to manufacturing yield. While variation is generally well understo... » read more

Using More Verification Cores
By Brian Bailey - 30 Aug, 2018 - Comments: 1

Semiconductor Engineering sat down to talk about parallelization efforts within EDA with Andrea Casotto, chief scientist for Altair; Adam Sherer, product management group director in the System & Verification Group of Cadence; Harry Foster, chief scientist for Mentor, a Siemens Business; Vladislav Palfy, global manager for applications engineering at OneSpin; Vigyan Singhal, chief Oski for ... » read more

Blog Review: Aug. 29
By Jesse Allen - 29 Aug, 2018 - Comments: 0

Mentor's Joe Hupcey III addresses inconclusive results in formal verification with tips on how to reduce the complexity of “assumption” properties to make them easier for the formal engines to digest and reach a solution. Cadence's Meera Collier looks beyond the immediate appeal of autonomous cars to the broader social implications of urban sprawl, public transit funding, and gentrificat... » read more

Partitioning Drives Architectural Considerations
By Ann Mutschler - 29 Aug, 2018 - Comments: 0

There are multiple reasons for design partitioning. One is complexity, because it’s faster and simpler to divide and conquer, particularly with third-party IP. A second reason involves power, where it may be more efficient to divide up functionality so each function be right-sized. A third involves performance, where memory utilization and processing can be split up according to functional pr... » read more

Is Software Necessary?
By Brian Bailey - 27 Aug, 2018 - Comments: 0

Hardware must be capable of running any software. While that might have been a good mantra when chips were relatively simple, it becomes an impossible verification task when dealing with SoCs that contain dozens of deeply embedded processors. When does it become necessary to use production software and what problems can that get you into? When verification targets such as power are added, it... » read more

Verification Trends Enabling A 5G Future
By Frank Schirrmeister - 23 Aug, 2018 - Comments: 0

Applications have driven requirements for verification for quite some time now, as I have written previously regarding Aero & Defense, AI and Machine Learning and the Internet of Things. In wireless communication, we are just at the brink of the transition to Fifth Generation Networks, or 5G. This transition will not only lead to new applications and use models that will impact our day-to-d... » read more

Big Changes For Mainstream Chip Architectures
By Ed Sperling - 23 Aug, 2018 - Comments: 3

Chipmakers are working on new architectures that significantly increase the amount of data that can be processed per watt and per clock cycle, setting the stage for one of the biggest shifts in chip architectures in decades. All of the major chipmakers and systems vendors are changing direction, setting off an architectural race that includes everything from how data is read and written in m... » read more

Blog Review: Aug. 22
By Jesse Allen - 22 Aug, 2018 - Comments: 0

Cadence's Paul McLellan considers how much further we need to go to make EUV work for 5nm, the problem of cost, and ASML's EUV roadmap. In a video, Mentor's Colin Walls explains optimizing data in embedded software with a simple example of two ways to put data in memory and how to decide which is best. Synopsys' Fred Bals provides a rundown of the different types of application security t... » read more

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