tag: Cadence

Week In Review: Design, Low Power
By Jesse Allen - 20 Sep, 2019 - Comments: 0

Tools & IP Synopsys debuted its new DesignWare ARC EV7x Embedded Vision Processor family for machine learning and AI edge applications. The ARC EV7x Vision Processors integrate up to four enhanced vector processing units (VPUs) and an optional Deep Neural Network (DNN) accelerator with up to 14,080 MACs to deliver up to 35 TOPS performance in 16nm FinFET process technologies under typical ... » read more

No Mess, No Stress
By Amit Varde - 18 Sep, 2019 - Comments: 0

A clean and tidy working environment is often a productive environment. Imagine a desk with a lot of clutter. One may lose precious work minutes every time we go searching for a lost paper on a cluttered desk. The same is true if you are working on your designs. During the course of a design project, spirited and fast thinking design engineers run several experiments. Some of them are more s... » read more

Why DRAM Won’t Go Away
By Ed Sperling - 18 Sep, 2019 - Comments: 0

Semiconductor Engineering sat down to talk about DRAM's future with Frank Ferro, senior director of product management at Rambus; Marc Greenberg, group director for product marketing at Cadence; Graham Allan, senior product marketing manager for DDR PHYs at Synopsys; and Tien Shiah, senior manager for memory marketing at Samsung Electronics. What follows are excerpts of that conversation. Part ... » read more

Blog Review: Sept. 18
By Jesse Allen - 18 Sep, 2019 - Comments: 0

Cadence's Paul McLellan checks out MLPerf and the challenges involved in developing a benchmark to assess machine learning training and inference performance. Synopsys' Om Prakash Thakur and Nusrat Ali take a look at the different types of NVDIMM and how it can bridge the performance gap between memory and storage solutions in servers. Mentor's Matthew Ballance points to why adoption of P... » read more

Scan Compression Is No Longer About Compression
By Rohit Kapur - 16 Sep, 2019 - Comments: 0

Scan compression was introduced in the year 2000 and has seen rapid adoption. Nearly every design’s test methodology today implements this technology, which inserts compression logic in the scan path between the scan I/Os and the internal chains. In this article, we take a critical look at the technology to understand how scan compression has matured. The road to scan compression Since th... » read more

3D Power Delivery
By Brian Bailey - 12 Sep, 2019 - Comments: 1

Getting power into and around a chip is becoming a lot more difficult due to increasing power density, but 2.5D and 3D integration are pushing those problems to whole new levels. The problems may even be worse with new packaging approaches, such as chiplets, because they constrain how problems can be analyzed and solved. Add to that list issues around new fabrication technologies and an emph... » read more

Trading Off Power And Performance Earlier In Designs
By Ann Mutschler - 12 Sep, 2019 - Comments: 0

Optimizing performance, power and reliability in consumer electronics is an engineering feat that involves a series of tradeoffs based on gathering as much data about the use cases in which a design will operate. Approaches vary widely by market, by domain expertise, and by the established methodologies and perspective of the design teams. As a result, one team may opt for a leading-edge des... » read more

Reducing Software Power
By Brian Bailey - 12 Sep, 2019 - Comments: 0

With the slowdown of Moore's Law, every decision made in the past must be re-examined to get more performance or lower power for a given function. So far, software has remained relatively unaffected, but it could be an untapped area for optimization and enable significant power reduction. The general consensus is that new applications such as artificial intelligence and machine learning, whe... » read more

Blog Review: Sept. 11
By Jesse Allen - 11 Sep, 2019 - Comments: 0

Cadence's Paul McLellan checks out the challenges of processing-in-memory and the steps involved in building a logic flow on a DRAM process. Synopsys' Taylor Armerding notes that with safety-critical software an ever-present factor in modern life, it's more necessary than ever to take the time to ensure quality and security when failures can be life-threatening. In a video, Mentor's Colin... » read more

How Hardware Can Bias AI Data
By Ed Sperling - 10 Sep, 2019 - Comments: 1

Clean data is essential to good results in AI and machine learning, but data can become biased and less accurate at multiple stages in its lifetime—from moment it is generated all the way through to when it is processed—and it can happen in ways that are not always obvious and often difficult to discern. Blatant data corruption produces erroneous results that are relatively easy to ident... » read more

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