tag: Cadence

Solving The Memory Bottleneck
By Brian Bailey - 04 Oct, 2019 - Comments: 4

Chipmakers are scrambling to solve the bottleneck between processor and memory, and they are turning out new designs based on different architectures at a rate no one would have anticipated even several months ago. At issue is how to boost performance in systems, particularly those at the edge, where huge amounts of data need to be processed locally or regionally. The traditional approach ha... » read more

ML, Edge Drive IP To Outperform Broader Chip Market
By Kevin Fogarty - 03 Oct, 2019 - Comments: 0

The market for third-party semiconductor IP is surging, spurred by the need for more specific capabilities across a wide variety of markets. While the IP industry is not immune to steep market declines in semiconductor industry, it does have more built-in resilience than other parts of the industry. Case in point: The top 15 semiconductor suppliers were hit with an 18% decline in 2019 first-... » read more

Blog Review: Oct. 2
By Jesse Allen - 02 Oct, 2019 - Comments: 0

In a video, Cadence's Tom Hackett explains finite element analysis by looking at a simple model of a bridge and showing why FEA techniques are required for analysis of real-world structures. Synopsys' Taylor Armerding examines why the 156-year-old False Claims Act has new relevance when companies are accused of failing to meet cybersecurity standards. Mentor's Colin Walls demystifies memo... » read more

Week In Review: Manufacturing, Test
By Mark LaPedus - 27 Sep, 2019 - Comments: 0

Chipmakers United Microelectronics Corp. (UMC) has satisfied all closing conditions for the full acquisition of Mie Fujitsu Semiconductor Ltd. (MIFS), the former 300mm wafer foundry joint venture between UMC and Fujitsu Semiconductor Ltd. (FSL). The completion of the acquisition is scheduled for Oct. 1. In 2014, FSL and UMC agreed for UMC to acquire a 15.9% stake in MIFS from FSL through pr... » read more

Week In Review: Design, Low Power
By Jesse Allen - 27 Sep, 2019 - Comments: 0

eSilicon debuted its 7nm high-bandwidth interconnect (HBI)+ PHY IP, a special-purpose hard IP block that offers a high-bandwidth, low-power and low-latency wide-parallel, clock-forwarded PHY interface for 2.5D applications such as chiplets. HBI+ PHY delivers a data rate of up to 4.0Gbps per pin. Flexible configurations include up to 80 receive and 80 transmit connections per channel and up to 2... » read more

Toward A Lingua Franca For Intelligent System Design
By Frank Schirrmeister - 26 Sep, 2019 - Comments: 1

As the EDA industry is moving up further and further towards the intelligent design of full systems, this year’s Forum on Design Languages (FDL) offered a great update on the status quo with regard to where languages fit into this transition. It looks like the next step will not be one universal language as previously targeted back when there was a flurry of introductions of new programming m... » read more

Open ISAs Gaining Traction
By Ann Mutschler - 26 Sep, 2019 - Comments: 0

Open instruction set architectures are starting to gain a foothold, often in combination with other processors, as chipmakers begin to add more specialized compute elements and more flexibility into their designs. There are a number of these open ISAs available today, including Power, MIPS, and RISC-V, and there are a number of permutations and tools available for sale based on those archite... » read more

The Growing Impact Of Portable Stimulus
By Brian Bailey - 26 Sep, 2019 - Comments: 0

It has been a year since Accellera's Portable Test and Stimulus Specification became a standard. Semiconductor Engineering sat down to discuss the impact it has had, and the future direction of it, with Dave Kelf, chief marketing officer for Breker Verification Systems; Larry Melling, product management director for Cadence; Tom Fitzpatrick, strategic verification architect for Mentor, a Siemen... » read more

Celsius Thermal Solver
By Cadence - 25 Sep, 2019 - Comments: 0

The Celsius Thermal Solver environment enables all aspects of thermal analysis to quickly and accurately identify thermal problems in IC packages, PCBs, and electronics systems. It features an innovative massive parallel solver technology that enables simulation speeds up to 10 times faster than conventional thermal simulators, with significantly reduced memory usage. It includes a powerful fin... » read more

Blog Review: Sept. 25
By Jesse Allen - 25 Sep, 2019 - Comments: 0

Mentor's Dave Rich points out that unexpected values from a constraint solver can often be explained by how Verilog expression evaluation rules affect the solution space of SystemVerilog constraints. Cadence's Madhavi Rao points to the need for new and updated safety and cybersecurity standards for autonomous vehicles and highlights one of the most challenging parts of AV deployment. A Sy... » read more

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