Open ISAs Gaining Traction

Emphasis on flexibility, time to market and heterogeneity requires more processing options.


Open instruction set architectures are starting to gain a foothold, often in combination with other processors, as chipmakers begin to add more specialized compute elements and more flexibility into their designs.

There are a number of these open ISAs available today, including Power, MIPS, and RISC-V, and there are a number of permutations and tools available for sale based on those architectures. What has opened the door to making these more acceptable in designs is that one or more of these architectures may be included in a chip alongside processors from Arm, Synopsys, Cadence, Achronix, Flex Logix, or even Intel.

There are a number of reasons why open ISAs make sense, and other reasons why they don’t make sense everywhere.

“The number one motivation is how to move faster,” said Steve Fields, IBM fellow and chief engineer of IBM Power Systems. “All of us who build chips and systems for a living spend so much time and energy and money rebuilding the same stuff. If I’m building an ASIC, I have to include a memory interface, and I have to put a control interface on it. They just need so many things that you occupy either engineering time or money, or both. That is the same stuff everybody else is putting on their chips, and whether I have to pay for a piece of silicon that does that job, or whether I can get it for free, the fact that I can just get it and focus my engineers on my special sauce is a huge value to anyone doing development.”

It’s also about the time it takes to do 20 agreements with 20 different IP houses, noted Mendy Furmanek, director of OpenPOWER processor enablement. “It’s become so cumbersome to go into building chips because of all these factors. At the same time, we really need the innovation. That’s why this [open ISA] movement is happening rapidly. We’ve got to get all of these barriers out of our way. It’s not just about money. It’s about all those things. But ultimately, it’s about faster innovation.”

The key is to figure out where commercial IP is needed, and where it isn’t. So while RISC-V is gaining momentum in the market, it has to be viewed in context of a system. And it takes some work on the part of the system developer to understand what exactly they’re getting.

“RISC-V is simply an open source ISA, which commercial IP providers implement into an IP product, then sell at industry-standard licensing and royalty models,” said Tim Whitfield, vice president of strategy for Arm’s Automotive and IoT business. “These offerings have limited differentiation, which forces IP providers to compete on price within their own ecosystem. In fact, when they do attempt to differentiate, software fragmentation could be a likely outcome, making it difficult for a coherent software ecosystem to grow around the ISA.”

Whitfield said RISC-V is moving through the classic “hype cycle.” For awhile it was the answer to everything – dollar-free IP, immune from security problems, customizable for any application and shielded from global trade wars.

“The reality, of course, has proven somewhat different,” he said. “Commercially, the RISC-V world is becoming characterized by IP companies offering CPU implementations through licensing and royalty models. There is very little that differentiates RISC-V from existing IP providers in terms of business model, whether it’s Synopsys and ARC, Cadence and Tensilica, or Arm. There is a significant financial consideration moving from ISA to processor IP, such as the cost of engineering, tools, compute, as well as a sizable software requirement. It’s the same for RISC-V as for any architecture. This is where having a mature ecosystem of common toolsets is invaluable when it comes to SoC design costs.”

Fig. 1: Ecosystem benefits for 28nm development. Source: Arm

Still, open ISAs ratchet up the competitive landscape, which pushes everyone to innovate across a number of fronts.

“Coca Cola needs Pepsi, and Intel absolutely needs AMD,” said Chris Jones, vice president of marketing at Codasip. “Otherwise, innovation is stifled and customers suffer economically. This especially holds true for processor IP. By the middle of the 2010s, consumers of processor IP were not exactly offered a lot of consumer choice. Thanks to a combination of the excellent execution of Arm, the acquisition and/or change in strategic focus of several of Arm’s erstwhile competitors, some macro trends, and serendipity, Arm was left standing alone.”

He believes this string of events hurt many in the semiconductor community because it limited their ability to differentiate among their competitors, effectively taxing their margins through royalty payments.

“The processor IP business is exceedingly difficult, and there were no true challengers to the throne,” Jones said. “Granted, this is not true for all. Many companies are served quite well by Arm and their products and models thanks to their predictability and stability. So they chose differentiate in other areas of chip design, be it accelerators, high speed interconnects, mixed signal expertise, etc., and conceded that the processor core is just the processor core. But for others trying to enter a highly competitive semiconductor market, licensing the same technology as everyone else is not a great starting point.”

Further, companies have become much more sensitive to vendor lock-in, where once a processor vendor is chosen, and millions of lines of software have been written for that processor, the costs of switching become far too high.

“RISC-V is the result of the semiconductor industry’s and open source community’s combined effort to establish an alternative architecture in the market to help alleviate the economic burden imposed by a single supplier market and to allow users to differentiate via processor optimization while still preserving their software investment and avoiding vendor lock,” Jones said. “Arm has countered the RISC-V existential threat by expanding the Design Start program to include the M3, to offering free cores for FPGA, to offering more attractive licensing terms for early access. These business moves were created to discourage customers from looking elsewhere for “entry-level” IP and have had the desired effect of putting downward pricing pressure on general embedded control processing, he said.

“Arm still holds a commanding technology lead for high-end applications processors, and whatever financial losses this model may incur can be compensated for at the high end,” he noted. “But RISC-V momentum continues to increase, because even if the economic challenge has been partially solved, the issue of differentiation remains. Custom processors represent the next logical step in architectural and power efficiencies. RISC-V’s modular architecture allows for elimination of extraneous logic without breaking software compatibility, and user-defined instructions can also be accommodated. And there is already a wide range of options in the market, from production-ready cores on GitHub, to commercial suppliers of RISC-V IP from companies like Andes and Codasip. These options will continue to expand, although certainly not all will be successful. Sophisticated users can choose to build their own microarchitectural implementation of a RISC-V core and toolchain, either from the ground up, or with the use of processor design tools from established suppliers like Synopsys or Codasip.”

Breaking it down
Discussions about open source ISAs often focus on perception, ecosystems and design methodologies. And even though it is commonly assumed that an open ISA implies free IP, it’s not that simple.

“While the semiconductor IP business model has established the license fee and royalties as a general principle, these are in fact complex and detailed agreements,” said Simon Davidmann, CEO of Imperas Software. “In addition to the fees involved, some effort is required to set up an agreement and negotiate all the contract details. The reality is that designing and verifying a processor is a significant task. Plus, there is the effort to develop and maintain all the software and ecosystem support required, so the comparison between an open ISA and a standard IP business mode is not as simple as make vs. buy.”

If a design or application requires new and optimized features that are not currently offered as IP cores, there are several options available. One is to ask the IP supplier to add/extend the core for a particular use case, which can be expensive. Building a complete core from scratch is even more expensive, although it can provide the best power and performance. A third option is to select an open ISA that allows some level of customization. In fact, the ‘free’ part of the open ISA is really about design freedom, Davidmann noted.

The open source model is well established in software. Similar approaches in hardware are starting to gain traction, but hardware can be much more difficult to optimize in a design. Still, an open ISA can be attractive option when sourced from a commercial IP vendor with support and services as attractive value-added options, he noted. In addition, many core providers also offer solutions to support custom optimizations with a range of tools and support from the growing ecosystem.

Design methodologies are a large consideration in this equation, and the selection process for a traditional IP business model involves significant benchmarking and evaluation. In addition, the deliverables are only available after the deal has closed. Due to the transactional impact, it’s more likely for a designer to configure a multicore design around just 1 or 2 base core options.

With an open ISA, options to evaluate a core for a design may well be as simple as downloading the deliverables from GitHub, and a multicore design could be based on almost infinite number of core alternatives, options and configurations. So faced with the instant access to an almost unlimited variety of cores, a system developer is now more likely to start with the application analysis and determine the real requirements and then consider the best available choices.

“This works well for virtual platforms, which allow tradeoffs in early design options with the freedom to model all available cores and configurations,” Davidmann said. “This functional specification approach also helps the design process with verification and early software development. In the past, the IP core may have been an early a central design decision. Now the system designer develops a functional spec and bases the key decisions around the actual application requirements instead of some artificial benchmark score.”

Perception depends on the datasheet visibility of the core, or key functionally for the device. In some markets, known software support is key, and highlighting IP brand names is an essential requirement for success. A strong community of users with an ecosystem of support has been the hallmark of successful processor adoption.

“Ecosystems are fundamentally about efficiency,” he added. “As a processor core becomes popular, the growing pool of developers and projects attracts ecosystem investment to develop tools and solutions to help them. This becomes a snowball effect as popularity drives more adoption and attracts more solutions across wider areas of requirements. Ultimately the value and efforts extended by the ecosystem can be a many-fold. The key is software reuse. But it’s a symbiotic relationship. Innovation on the processor needs to evolve and include support from the ecosystem. This cannot be forced. There are many examples of hardware innovation that failed to gain the critical mass of ecosystem support or migrate successes in one market segment to another. An open ISA has the one advantage over traditional IP approaches in that, while it may not have a roadmap in detail pre-defined, it has a structure that permits optimization and customization. If the ecosystem can fully support this inherent flexibility, any new hardware should see less barriers to future adoption.”

New opportunities with open ISAs
For EDA companies, open ISAs are an opportunity to sell more tools using an infrastructure for disparate processors. But these open ISAs also change some of the dynamics with customers,

“If you look at the first and most important decision you had to make when building an SoC, it was to pick your processors,” said Neil Hand, director of marketing for IC verification solutions at Mentor, a Siemens Business. “Then you would build up the rest of the architecture and eventually get the system up and running. But there’s a limit to what you can do. With an ISA like RISC-V, much like with people choosing an Arm processor, once they have that generic definition they can pick the specific processor later on. In the case of RISC-V, once you’ve got most of your system there, you can then go and benchmark 5 or 10 different providers to see which one gives you the best performance, given your unique design. That’s something that wasn’t possible even with the leading standard processor providers. You couldn’t benchmark a Tensilica versus a MIPS versus an ARC versus anything else because the amount of infrastructure that you need to change just wouldn’t allow you to do that, whereas within that common infrastructure of RISC-V you can.”

There are other advantages, too. “If you are a processor IP company, the amount of effort you’ve got to put in to get your whole tool stack together, to get your operating systems ported, to get your EDA infrastructure for the customers with instruction set simulators, virtual models — all this is huge,” Hand said. “You’re probably orders of magnitude more than the processor design itself. And if you’ve got a great idea for an ML-based RISC-V accelerator, and you’re going to be blending in some ML instructions in there, you don’t need to go build a compiler. You can use one of the standard compilers. You might have to extend it, but it’s a fraction of the work that would be there otherwise.”

It’s the same with the Power ISA, Furmanek explained, “That’s the beauty of Power – we actually have all that. We’re coming from the other direction, and we have built that whole ecosystem. Open Power started with the focus in the system arena and up the stack. IBM has had a long history in ‘open’ going back to the founding of the Linux Foundation. It’s in our DNA, so we’ve built that full ecosystem out and said now’s the time to go further, open up the instruction set, and really start building hardware devices off that instruction set and get more built on Power in this open hardware landscape. We’ve got the ecosystem to run it.”

And while the Power PC was known at the very high end, it’s now being used for more cost-sensitive applications. This has actually given new life to the Power ISA for companies that previously implemented it in mobile or PowerPC applications, and which have legacy technology that can be resurrected.

It’s the same with SystemC models for virtual prototyping and so on, Hand said. “So you don’t have to build that infrastructure, which gives you more resources to go into the core innovation that is there. For consumers, it takes the risk out of it, so no one ever worries about buying an Arm processor, for instance, and the company’s there with a solid infrastructure. Everything is all good. And if you’re going to go buy a processor from some relatively young, unknown startup, you’re going to be worried about it. But if you know that you can switch out that processor for another fully compatible processor from another vendor, that concern goes away.”

Allen Baker, lead software developer on the semiconductor business unit at ANSYS, stressed that even though RISC-V is still in its early stages, it has proven to be beneficial in interacting with potential customers.

“While a minority of users are actively using it, there was a recent example in which a potential user was using an open source implementation of RISC-V called the Rocket core open source design,” Baker said. “They are basing some of their products on it, so they were interested in our solutions. We were actually able to, for probably the first time, attain this Rocket core ourselves. Because it’s open source, it’s hosted on GitHub, so we can just download that, run it through the tools ourselves to prepare demos prior to going to them to explain how our tools work and how they can be useful for their analysis. We’ve never been able to do that before, actually showing how our tools work on something that they are working on. They’re a potential user, so we’ve had very little communication with them, and normally we’d need a history with our users to even consider sharing IP with us to run internally. This is exactly what I want to have happen more often with these open-source implementations.”

Baker said the surprising part is that these open source implementations are actually being heavily used in production. “They’re not just research projects. These are real designs that people are basing their businesses on, so if you’re able to also add easy access to them to develop new tools or extensions, your work is immediately relevant to this broad ecosystem.”

Jens Warmuth, group leader, functional safety and system reliability at Fraunhofer IIS/EAS agreed that RISC-V offers big advantages like avoiding the use of license-based and therefore expensive “blackbox” processor IPs. “Additionally, it enables compliance with functional safety requirements for both hardware and software due to its open architecture. Therefore, the development and usage of a large number of RISC-V derivates for every conceivable use case can be expected in the near future, due to many design houses deciding to develop their own special RISC-V processor derivation IP. Because of this, the software development and validation based on these IPs will become a challenge at an early product state. The acceleration in the product development while maintaining guaranteed functional safety will decide a company’s success more than nowadays.”

In this light, Fraunhofer is able to synthesize the IP for an FPGA of a real-time platform and to embed it into a heterogeneous model-based virtual system environment, which allows for the validation of the target object code in a real-time environment very early in the design process and very close to the later use case.

While it’s not an either/or type of decision, open ISAs are gaining traction. “System companies that don’t embrace this are going to be constrained in the future,” said IBM’s Fields. “To what extent, and how quickly that happens, is up for debate. But it’s going to happen.”

Behind all of this is a shift toward more heterogeneity and customization, both of which will be required as the industry begins to address the next era of computing.

“This is characterized by even greater connectivity enabled by 5G, coupled with the need for intelligence on the edge,” said Arm’s Whitfield. “This distributed, heterogeneous compute is driving a requirement for more efficient, application-specific silicon. To enable this, we will need to see higher levels of design automation and growth in shared innovation platforms to create custom silicon solutions.”

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