tag: Cadence

Test On New Technology’s Frontiers
By SE Staff - 10 Sep, 2019 - Comments: 2

Semiconductor testing is getting more complicated, more time-consuming, and increasingly it requires new approaches that have not been fully proven because the technologies they are addressing are so new. Several significant shifts are underway that make achieving full test coverage much more difficult and confidence in the outcome less certain. Among them: Devices are more connected an... » read more

Autonomous Vehicles Are Reshaping The Tech World
By Kevin Fogarty - 05 Sep, 2019 - Comments: 0

The effort to build cars that can drive themselves is reshaping the automotive industry and its supply chain, impacting everything from who defines safety to how to ensure quality and reliability. Automakers, which hardly knew the names of their silicon suppliers a couple of years ago, are now banding together in small groups to share the costs and solve technical challenges that are well be... » read more

The Race For Better Computational Software
By Ed Sperling - 05 Sep, 2019 - Comments: 0

Anirudh Devgan, president of Cadence, sat down with Semiconductor Engineering to talk about computational software, why it's so critical at the edge and in AI systems, and where the big changes are across the semiconductor industry. What follows are excerpts of that conversation. SE: There is no consistent approach to how data will be processed at the edge, in part because there is no consis... » read more

IP’s Growing Impact On Yield And Reliability
By Ann Mutschler - 04 Sep, 2019 - Comments: 0

Chipmakers are finding it increasingly difficult to achieve first-pass silicon with design IP sourced internally and from different IP providers, and especially with configurable IP. Utilizing poorly qualified IP and waiting for issues to appear during the design-to-verification phase just before tape-out can pose high risks for design houses and foundries alike in terms of cost and time to... » read more

A Complete System-Level Security Verification Methodology
By Cadence - 04 Sep, 2019 - Comments: 0

Hardware is at the root of all digital systems, and security must be considered during the system-on-chip (SoC) design and verification process. Verifying the security of an SoC design is challenging because of time to market pressure and resource constraints. Resources allocated to the already time-consuming task of functional verification must be diverted to security verification, which requi... » read more

New Technologies To Support 3D-ICs
By Brian Bailey - 04 Sep, 2019 - Comments: 0

Semiconductor Engineering sat down to discuss changes required throughout the ecosystem to support three-dimensional (3D) chip design with Norman Chang, chief technologist for the Semiconductor Business Unit of ANSYS; John Park, product management director for IC packaging and cross-platform solutions at Cadence; John Ferguson, director of marketing for DRC applications at Mentor, a Siemens Bus... » read more

Blog Review: Sept. 4
By Jesse Allen - 04 Sep, 2019 - Comments: 0

Synopsys' Taylor Armerding checks out Apple's newly expanded bug bounty program, with bounty payouts are increasing to compete with malicious actors, and why even with security-oriented development the practice of bug bounties will remain needed. Mentor's Colin Walls shares a few more embedded software tips, this time on external variables, delay loops in real time systems, and meaningful pa... » read more

On The Cusp Of 5G
By Kevin Fogarty - 29 Aug, 2019 - Comments: 0

Carriers and chipmakers are celebrating the rollout of the first standards-compliant commercial 5G services. "We are, officially in the era of 5G," said John Smee, vice president of engineering at Qualcomm at the recent 5G Summit at IEEE's International Microwave Symposium (IMS) in Boston. Movement is happening on the commercial end. Major U.S. carriers Verizon, AT&T and Sprint have set ... » read more

Taking Energy Into Account
By Ann Mutschler - 28 Aug, 2019 - Comments: 1

Considering power throughout the SoC design flow is common practice. The same cannot be said for energy, although that is beginning to change as chips increasingly incorporate heterogeneous processing elements. Combined with this, AI/ML/DL technologies increasingly allow engineering teams to explore and optimize design data for more targeted and efficient systems. But this approach also requ... » read more

Blog Review: Aug. 28
By Jesse Allen - 28 Aug, 2019 - Comments: 0

Cadence's Paul McLellan takes a look at the numerous challenges in designing and manufacturing Cerebras' massive 400,000 processor, 1.2 trillion transistor chip. Synopsys' Taylor Armerding points to a lack of robust mobile app security and why building in security from the beginning can lead to greater productivity and cost saving. Mentor's Paul Johnston takes a look at what's in store at... » read more

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