tag: Cadence

Solutions For Mixed-Signal SoC Verification
By Various Writers - 28 Mar, 2013 - Comments: 0

Performing full-chip verification of large mixed-signal systems on chip (SoCs) is an increasingly daunting task. As complexity grows and process nodes shrink, it’s no longer adequate to bolt together analog or digital “black boxes” that are presumed to be pre-verified. Complex analog/ digital interactions can create functional errors, which delay tapeouts and lead to costly silicon re-spi... » read more

Solutions For Mixed-Signal IP, IC, And SoC Implementation
By Various Writers - 28 Mar, 2013 - Comments: 0

Traditional mixed-signal design environments, in which analog and digital parts are implemented separately, are no longer sufficient and lead to excess iteration and prolonged design cycle time. Realizing modern mixed-signal designs requires new flows that maximize productivity and facilitate close collaboration among analog and digital designers. This paper outlines mixed-signal implem... » read more

Trying To Catch Up With Software Developers
By Frank Schirrmeister - 27 Mar, 2013 - Comments: 0

By Frank Schirrmeister The electronic design automation (EDA) industry has now been trying for at least a decade and a half to catch up with software developers, for two main reasons. First, there are so many of them that it would be great to expand EDA into that domain. Second, semiconductor companies, i.e. the core customers to which the EDA industry sells, have had to add more and more soft... » read more

Verifying Your Intent
By Ann Mutschler - 21 Mar, 2013 - Comments: 0

Design rule checking (DRC), layout versus schematic (LVS) and electrical rule checking (ERC) are physical verification techniques that are mandatory today to check a design and its structures before manufacturing. Checking electrical characteristics of a design is one thing. Verifying power intent is quite another. And the overlap of the two is an intriguing concept. Case in point: Checking fo... » read more

Next-Generation Signoff Analysis
By Various Writers - 21 Mar, 2013 - Comments: 0

The electronic design industry continues to push the limits of moore's law through smaller and smaller process nodes. As we reach 45nm, manufacturing and process control becomes increasingly difficult, making it imperative that manufacturability issues be addressed much earlier in the design cycle to avoid costly respins and chip failures. Physical and electrical effects at this node challen... » read more

A Balancing Act
By Ann Mutschler - 14 Mar, 2013 - Comments: 0

By Ann Steffora Mutschler If you stay current on data center trends, you are well-versed on the fact that Intel reported last June energy proportionality has effectively doubled server efficiency and workload scaling beyond what Moore’s Law predicted. What does this have to do with power management of SoCs? Cary Chin, director of marketing for low-power solutions at Synopsys, said tha... » read more

Sprint To The Finish Line
By Ed Sperling - 14 Mar, 2013 - Comments: 0

By Ed Sperling Low-Power/High-Performance Engineering sat down to discuss future challenges, pain points, and how the supply chain is being reconfigured with Chi-Ping Hsu, senior vice president for R&D in the Silicon Realization Group at Cadence. What follows are excerpts of that conversation. LPHP: How important is it to be at the front end of Moore’s Law? Hsu: Strategically, it’... » read more

Moore’s Law 2.0
By Ed Sperling - 14 Mar, 2013 - Comments: 0

By Ed Sperling Doubling the number of transistors on a piece of silicon every 18 to 24 months used to be synonymous with engineering progress, but as the semiconductor world migrates from processors to SoCs the fundamental basis of Moore’s Law is losing its meaning. Even its famous timetable is slipping. For one thing, it’s simply too expensive and difficult to migrate from one node to ... » read more

Version Control
By Ed Sperling - 14 Mar, 2013 - Comments: 0

By Ed Sperling & Ann Steffora Mutschler One of the biggest impediments to progress in semiconductor design is progress itself—version after version of specifications, formats and increasingly IP. In fact, there are so many different versions, some of which conflict directly with each other, that it may take months or even years before some customers adopt new products. Much has ... » read more

Let The IP Wars Begin
By Ed Sperling - 14 Mar, 2013 - Comments: 0

y Ed Sperling Nature abhors a vacuum. Customers abhor a monopoly. It appears both problems are now being solved in the EDA world—assuming approval by regulatory agencies, of course. There have been two concerns facing chipmakers in regards to third-party IP. One is political. Most large companies spent millions of dollars and thousands of frustrating man-hours developing their own interna... » read more

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