tag: Cadence

The Week In Review: Manufacturing
By Mark LaPedus - 14 Mar, 2014 - Comments: 0

SanDisk filed a civil suit against Korea’s SK Hynix. Additionally, SanDisk has submitted a criminal complaint with the Tokyo Metropolitan Police Department against a former employee. These actions relate to the theft of trade secrets related to NAND flash technology by a former engineer of SanDisk who left the company in 2008 to work for SK Hynix. Cadence Design Systems and GlobalFoundrie... » read more

The Next Bigger Things
By Ed Sperling - 13 Mar, 2014 - Comments: 0

When the Internet of Things really started making headlines several years ago—the concept had been around since at least the early 1990s—the assumption was that most of the semiconductors involved in sensing and communicating would be simple, highly limited, and developed using older technology. As the concept evolves and grows, however, it’s beginning to take on a whole new texture. R... » read more

High Level Synthesis Grows Up
By Brian Bailey - 13 Mar, 2014 - Comments: 2

When Semiconductor Engineering proposed this Experts At The Table discussion, which was held at the recently concluded DVCon, [getentity id="22032" e_name="Cadence"] had yet to express its intention to purchase [getentity id="22087" e_name="Forte"]. Little did we know that the stakes in the [gettech id="31015" comment="high-level synthesis"] (HLS) arena were being raised so high. Is this an in... » read more

Do We Need A “Glue” Engineer?
By Brian Fuller - 13 Mar, 2014 - Comments: 0

Design and verification are so complex today and fraught with market risk that it keeps managers awake and sweating at night. So much of design is carved up in IP blocks and subsystems, each with their own verification issues and methodologies. To manage the complexity the design is partitioned, and so too are the teams. But as software verification becomes more crucial to system-design succ... » read more

Know What To Look For
By Ann Mutschler - 13 Mar, 2014 - Comments: 0

With the number of power domains exploding in today’s ICs, it’s extremely difficult to include all different modes of complexity in the verification. “The problem was already challenging enough,” observed Mark Baker, director of product marketing at Atrenta. “Just looking at where SoC design was going was a collection of various IPs, the different communication protocols, the bus ... » read more

Automation Can’t Replace Human Intervention
By Ann Mutschler - 13 Mar, 2014 - Comments: 0

We work in a dynamic industry where the focus is on making it easier to design and verify semiconductor chips by automating tasks for the design engineer. There is so much emphasis on this that I wonder if it is easy to forget the value of that designer’s experience. No matter how automated a process gets, there is always the fundamental assumption that the engineer knows what is happening be... » read more

Pointing Fingers In Verification
By Brian Bailey - 12 Mar, 2014 - Comments: 11

With most EDA tools, the buying decision is related to improved quality of results or increased productivity. Will a new synthesis or clock optimization tool enable designers to do more, faster and are those gains worth the price? The equation is fairly simple. When it comes to verification tools, things are more complex. You can still make productivity gains, or purchase an additional tool ... » read more

Five Key Challenges In Designing With High-Speed Analog IP
By Various Writers - 12 Mar, 2014 - Comments: 0

There’s good reason why analog IC design is often considered to be more of an art than a science. Compared to their digital counterparts, analog components are much more sensitive to noise, distortion, and other errors. This white paper is filled with tips on meeting these challenges and speeding up your design cycle. To download this paper, click here. » read more

Blog Review: March 12
By Ed Sperling - 12 Mar, 2014 - Comments: 0

Arteris’ Kurt Shuler is sounding the alarm bell for the semiconductor industry. He observes that system OEMs are hiring their own chip engineers. Well, that should wake up someone. Danger Will Robinson. Mentor’s Colin Walls points to a festering debate in the embedded software world about priorities and openness to learning new tools and approaches. Embedded software developers are a rat... » read more

The Week In Review: Design
By Ed Sperling - 07 Mar, 2014 - Comments: 0

Tools Synopsys rolled out a new version of its software technologies for static and formal verification, which it says increases performance by up to five times. Also new are improved debug and low-power verification with native power simulation, and an integrated IP portfolio. Cadence uncorked a new version of its PCB and packaging environment, which it says speeds up timing closure by as ... » read more

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