Raising IP Integration Up A Level

By Brian Bailey - 27 Oct, 2022 - Comments: 0

An increase in the number and complexity of IP blocks, coupled with changing architectures and design concerns, are driving up the need for new tools that can enable, automate, and optimize integration in advanced chips and packages. Power, security, verification and a host of other issues are cross-cutting concerns, and they make pure hierarchical approaches difficult. Adding to future comp... » read more

Fabless IDMs Redefine The Leading Edge

By Marie C. Baca - 27 Oct, 2022 - Comments: 0

Large systems companies are looking more like integrated device manufacturers, designing their own advanced chips, packages, and systems for internal use. But because these are not pure-play chip companies, they are disrupting a 10-year cadence of customization and standardization that has defined the chip industry from its inception, and extending the period of innovation without the associate... » read more

AI-Driven Big Data Analytics Enables Actionable Intelligence, Improving SoC Design Productivity

By Cadence - 26 Oct, 2022 - Comments: 0

As the latest systems on chip (SoCs) grow in size and complexity, a vast amount of design data is generated during verification and implementation. Design data is business critical and, with the proliferation of artificial intelligence (AI) use in chip design, provides designers an opportunity to carry forward learnings and insights with every new design. To achieve first-pass success deliverin... » read more

Blog Review: Oct. 26

By Jesse Allen - 26 Oct, 2022 - Comments: 0

Synopsys' Teng-Kiat Lee and Sandeep Mehndiratta argue that IC design in the cloud can support an existing on-prem strategy, enable large and small enterprises to manage cost and capacity more effectively, and offer security for valuable semiconductor IP. Siemens EDA's Chris Spear finds that SystemVerilog classes are a good way to encapsulate both variables and the routines that operates on t... » read more

Chip Challenges In The Metaverse

By Marie C. Baca and Ed Sperling - 24 Oct, 2022 - Comments: 0

The metaverse is pushing the limits of chip design, despite uncertainty about how much raw horsepower these devices ultimately will require to deliver an immersive blend of augmented, virtual, and mixed reality. The big challenge in developing these systems is the ability to process mixed data types in real time while the data moves uninterrupted at lightning speed. That requires the integra... » read more

Bespoke Silicon Rattles Chip Design Ecosystem

By Ann Mutschler - 19 Oct, 2022 - Comments: 0

Bespoke silicon developers are shaking up relationships, priorities, and methodologies across the semiconductor industry, creating demand for skills that cross traditional boundaries, and driving new business models that leverage these enormous investments. Bespoke silicon designers today are a rare breed, capable of understanding the unique requirements of a specific domain, as well as a gr... » read more

Blog Review: Oct. 19

By Jesse Allen - 19 Oct, 2022 - Comments: 0

Siemens EDA's Harry Foster examines trends related to various aspects of FPGA design and the growing design complexity associated with increasing number of embedded processor cores, asynchronous clock domains, and more safety features. Synopsys' Twan Korthorst and Kenneth Larsen take a broad look at silicon photonics, including the benefits of electronic integration, accelerating the develop... » read more

Complex Tradeoffs In Inferencing Chips

By John Koon - 17 Oct, 2022 - Comments: 0

Designing AI/ML inferencing chips is emerging as a huge challenge due to the variety of applications and the highly specific power and performance needs for each of them. Put simply, one size does not fit all, and not all applications can afford a custom design. For example, in retail store tracking, it's acceptable to have a 5% or 10% margin of error for customers passing by a certain aisle... » read more

Week In Review: Design, Low Power

By Jesse Allen - 14 Oct, 2022 - Comments: 0

Cadence unveiled a new environment to automate and accelerate the complete design closure cycle from signoff optimization through routing, static timing analysis (STA), and extraction. The Certus Closure Solution allows concurrent, full-chip optimization through a massively parallel and distributed architecture and engine shared with Cadence’s Innovus Implementation System and the Tempus Timi... » read more

Heterogeneous Integration Co-Design Won’t Be Easy

By Tom Beckley - 13 Oct, 2022 - Comments: 0

The days of “throwing it over the wall” are over. Heterogeneous integration is ushering in a new era of silicon chip design with collaboration at its core—one that lives or dies on seamless interaction between your analog and digital IC and package design teams. Heterogeneous integration is the use of advanced packaging technologies to combine smaller, discrete chiplets into one syste... » read more

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Knowledge Centers
Entities, people and technologies explored

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

Legacy Process Nodes Going Strong

The critical, and growing, significance of mature node chips and processes.

by Bryon Moyer

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

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