tag: Cadence

Blog Review: May 22
By Jesse Allen - 22 May, 2024 - Comments: 0

Cadence's Sree Parvathy introduces Verilog-A, a high-level language that uses modules to describe the structure and behavior of analog systems and enables the top-down system to be defined before the actual transistor circuits are assembled. Siemens' Keith Felton suggests the process of package substrate design is improved by leveraging the collective expertise of multiple design domain spec... » read more

Chip Aging Becoming Key Factor In Data Center Economics
By Ann Mutschler - 20 May, 2024 - Comments: 1

Chip aging is becoming a much bigger concern inside of data centers, where it can impact server uptime, utilization rates, and the amount of energy needed to drive signals and cool entire server racks. Aging in chips is the result of both higher logic utilization and increasing transistor density. This is problematic for data centers, in general, but especially for AI chips where digital log... » read more

How Quickly Can You Take Your Idea To Chip Design?
By Kira Jones - 16 May, 2024 - Comments: 0

Gone are the days of expensive tapeouts only done by commercial companies. Thanks to Tiny Tapeout, students, hobbyists, and more can design a simple ASIC or PCB design and actually send it to a foundry for a small fraction of the usual cost. Learners from all walks of life can use the resources to learn how to design a chip, without signing an NDA or installing licenses, faster than ever before... » read more

Three Ways To Speed Up Timing Closure Of High-Speed PCB Interfaces
By Cadence - 15 May, 2024 - Comments: 0

On advanced high-speed interfaces, timing closure can be an iterative process that can be time-consuming and frustrating. PCB designers need techniques and tools to make the process more efficient, so they can contribute to an overall faster time to market for the design. This article discusses three ways that the new Cadence Allegro TimingVision environment speeds up timing closure of high-spe... » read more

Blog Review: May 15
By Jesse Allen - 15 May, 2024 - Comments: 0

Cadence's Anika Sunda suggests that RISC-V has opened numerous doors for innovation and believes EDA tools can help bridge the knowledge gap and foster a growing community of RISC-V developers. Synopsys' Alessandra Costa chats with industry experts about challenges facing analog design, what's needed for multi-die designs, and the potential of AI. Siemens' Bill Ji explains why understandi... » read more

Software-Defined Vehicle Momentum Grows
By Ann Mutschler - 09 May, 2024 - Comments: 0

Experts at the Table: The automotive ecosystem is undergoing a transformation toward software-defined vehicles, spurring new architectures with more software. Semiconductor Engineering sat down to discuss the impact of these changes with Suraj Gajendra, vice president of products and solutions in Arm's automotive line of business; Chuck Alpert, R&D automotive fellow at Cadence; Steve Spadon... » read more

UCIe And Automotive Electronics: Pioneering The Chiplet Revolution
By Vinod Khera - 09 May, 2024 - Comments: 0

The automotive industry stands at the brink of a profound transformation fueled by the relentless march of technological innovation. Gone are the days of the traditional, one-size-fits-all system-on-chip (SoC) design framework. Today, we are witnessing a paradigm shift towards a more modular approach that utilizes diverse chiplets, each optimized for specific functionalities. This evolution pro... » read more

Blog Review: May 8
By Jesse Allen - 08 May, 2024 - Comments: 0

Synopsys' Manuel Mota and Michael Posner look to UCIe as a complete stack for the die-to-die interconnect in multi-die chip designs, finding it can help maintain latency while reducing power and enhancing performance along with providing assurance of interoperability. Cadence's Durlov Khan highlights the Octal SPI interface for serial NAND flash, which enables 8-bit wide high bandwidth synch... » read more

CMOS Noise Margin Values
By Cadence - 08 May, 2024 - Comments: 0

One of the most important parameters describing digital systems operating at high speed is noise margin. In a general sense, noise margins define an acceptable level of noise that can be present on an I/O pin or in an interface. In terms of digital electronics, noise margin characterizes the level of noise that can appear on an I/O pin without creating an error in a received logic state. This i... » read more

Communication Is Key To Finding And Fixing Bugs In ICs
By Ann Mutschler and Adam Kovac - 08 May, 2024 - Comments: 0

Experts at the Table: Finding and eliminating bugs at the source can be painstaking work, but it also can prevent even greater problems from developing later on. To examine the best ways to tackle this problem, Semiconductor Engineering sat down with Ashish Darbari, CEO at Axiomise; Ziyad Hanna, corporate vice president R&D at Cadence; Jim Henson, ASIC verification software product manager ... » read more

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