Blog Review: Aug. 13

By Ed Sperling - 13 Aug, 2014 - Comments: 0

Cadence’s Richard Goering interviews Kathryn Kranen about the acquisition of her company, along with the business of formal verification. Interesting tidbit: The combined company has more than 50% market share in formal. Mentor’s John Day looks at Volkswagen’s upcoming all-electric Golf that will go on sale later this year in the United States. The new twist: VW has struck a deal with ... » read more

The Week In Review: Design

By Ed Sperling - 08 Aug, 2014 - Comments: 0

Tools Cadence rolled out a custom power integrity tool for dealing with transistor-level electromigration and IR drop with SPICE-level accuracy. It works in conjunction with the company’s existing power integrity tool for cell-level power signoff. Open-Silicon established a high-speed SerDes technology center of excellence to speed design and production of ASICs using high-speed serial co... » read more

IP Reaches Back To Established Nodes

By Ann Mutschler - 07 Aug, 2014 - Comments: 0

Driven by the [getkc id="76" kc_name="IoT"] and wearable market opportunity, [getkc id="81" kc_name="SoC"] developers are shifting backward to established nodes, and what is learned at the leading-edge nodes is being leveraged in reverse as IP is ported backward to improve functionality. [getkc id="43" kc_name="IP"] certainly can be improved to work faster at older geometries, stressed Krish... » read more

Established Nodes Getting New Attention

By Ed Sperling - 07 Aug, 2014 - Comments: 0

As the price of shrinking features increases below 28nm, there has been a corresponding push to create new designs at established nodes using everything from near-threshold computing to back biasing and mostly accurate analog sensors. The goals of power, performance and cost haven’t changed, but there is a growing realization among many chipmakers that the formula can be improved upon with... » read more

Creating A Strategy For Power Reduction In ICs

By Rob Eccles - 07 Aug, 2014 - Comments: 0

In last month’s blog, various power saving techniques were presented. These different techniques fit into three categories: gross (or coarse-grain) design, fine-grain design, and fine-grain process. In this blog, different techniques will be compared. By understanding the different techniques, it will become clear which ones to use in your design. Fine-grain process techniques For ... » read more

LP SoC Design: Part 2

By Anand Iyer - 16 Jul, 2014 - Comments: 0

In my last blog I talked about why designers need to rethink their methodology for low-power design and also introduced gross and fine-grain low power techniques. In this blog I am going to compare and contrast these techniques. Low-power design techniques fall under two categories, gross and fine-grain. Gross techniques are not dependent on the design or the process. Techniques such as powe... » read more

After Moore’s Law: More With Less

By Brian Bailey - 10 Jul, 2014 - Comments: 6

In the decades when Moore’s Law went unquestioned, the industry was able to migrate to the next smaller node and receive access to more devices that could be used for increased functionality and additional integration. While less significant transistor-level power savings have been seen from the more recent nodes, as leakage currents have increased, the additional levels of integration have b... » read more

Raising The Abstraction Of Power: Trends

By Ann Mutschler - 10 Jul, 2014 - Comments: 0

Given that design requirements for today’s SoCs go well beyond performance and area, energy efficiency and its impact on system design plays a major role for many end applications ranging from wireless sensor networks to autonomous vehicles as well as emerging applications in the Internet of Things market segment, where cooling capability is limited and expensive. For these reasons, a comp... » read more

Supporting LP In New Process Nodes

By Ann Mutschler - 10 Jul, 2014 - Comments: 0

Manufacturing process nodes and EDA tools are advancing all the time, but not always utilized at the same pace. And from a tools perspective, there are challenges to supporting low power in new process nodes while maintaining and improving the existing process nodes. One way design teams address this is by leveraging the most advanced software on the less-than-bleeding edge designs. To th... » read more

RTL Power Reduction And High Level Synthesis Report 2013

By Calypto - 09 Jul, 2014 - Comments: 0

This report covers trends in the area of low-power design and C-based design. The report analyzes the survey results of 648 engineers and engineering managers and identifies relevant emerging trends. To view this white paper, click here. » read more

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Knowledge Centers
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