tag: CDC

Multi-Mode Clock Domain Crossing Verification Enables Analysis Efficiency And Accuracy
By Mentor, a Siemens Business - 29 Jul, 2020 - Comments: 0

This paper shows how automated modal CDC analysis is used to exhaustively verify CDC issues in all test and operational modes of an SoC with multiple IPs. This new approach automatically consolidates all results from each mode, making issues very easy to interpret and debug. What took days and weeks with the prior manual approach now takes only a few hours. To read more, click here. » read more

Maximizing Value Post-Moore’s Law
By Brian Bailey - 13 Jul, 2020 - Comments: 0

When Moore's Law was in full swing, almost every market segment considered moving to the next available node as a primary way to maximize value. But today, each major market segment is looking at different strategies that are more closely aligned with its individual needs. This diversity will end up causing both pain and opportunities in the supply chain. Chip developers must do more with a ... » read more

Eliminate Silicon Respins With Netlist CDC Verification
By Synopsys - 24 Jun, 2020 - Comments: 0

Clock domain crossing (CDC) verification has been an integral part of modern chip design flow for quite sometime. Traditionally CDC verification has been done during the RTL stage. However, for advanced designs and complex flows, there is significant logic optimization during RTL synthesis as well as backend flows at the netlist stage. This mandates clock domain crossing verification a must for... » read more

Constraint-Based Verification Of Clock Domain Crossings
By Synopsys - 25 Mar, 2020 - Comments: 0

There are many measures of the ever-growing size and complexity of semiconductor devices: die area, transistor count, gate count, size of memories, amount of parallel processing and more. All these factors mean more time spent in design, but they also have a major impact on verification. Since virtually all industry studies show verification time and effort growing faster than design, this impa... » read more

Manufacturing Bits: March 9
By Mark LaPedus - 09 Mar, 2020 - Comments: 0

Finding cures for coronavirus The Department of Energy’s Oak Ridge National Laboratory (ORNL) is using the world’s most powerful supercomputer to identify drug compounds and cures for the coronavirus. [caption id="attachment_24162601" align="alignleft" width="300"] Summit supercomputer. Source: Oak Ridge National Laboratory[/caption] The supercomputer, called Summit, has identified 7... » read more

An Industry Under Siege
By Ed Sperling - 05 Mar, 2020 - Comments: 0

The coronavirus is taking a big toll on the semiconductor industry's unquenchable thirst for new information. The longer it lasts, the more the industry will have to resort to technology — some new, some old — to continue moving forward. Over the past couple weeks, conferences and trade shows have been postponed or outright canceled. Synopsys, Cadence and Intel pulled out of DVCon at the... » read more

Fusing Implementation And Verification
By Ed Sperling - 02 Mar, 2020 - Comments: 0

Susantha Wijesekara, senior application engineer at Synopsys, drills down into how to re-use Tcl scripts for static verification, what needs to be done with those scripts to make that possible, why that is critical to “shift left,” and how that approach saves time, money, and improves quality. » read more

Dynamic CDC Jitter For Clock Domain Crossing (CDC) Signoff
By Himanshu Bhatt - 16 Jan, 2020 - Comments: 0

By Himanshu Bhatt and Paras Mal Jain Detecting and debugging deep sequential CDC convergences using structural CDC verification is extremely difficult since doing a flat analysis on large designs has capacity related challenges, and even if verification tools can complete the analysis, it becomes a nightmare to debug the violations with complex sequential logic. Thus arises the need for dyna... » read more

Shift Left Power-Aware Static Verification
By Himanshu Bhatt - 10 Oct, 2019 - Comments: 0

Next-generation SoCs with advanced graphics, computing, machine learning (ML) and artificial intelligence (AI) capabilities are posing new unseen challenges in Low Power Verification. These techniques can introduce critical bugs into a design, especially when the power-management infrastructure interacts with signals that cross clock or reset domains. This can create additional clock-domain cro... » read more

Clock Domain Crossing Signoff Through Static-Formal-Simulation
By Sudeep Mondal - 22 Aug, 2019 - Comments: 0

By Sudeep Mondal and Sean O'Donohue Clocking issues are one of the most common reasons for costly design re-spins. This has been the driving factor in the ever-increasing demand for Clock Domain Crossing (CDC) analysis tools. Today, the majority of IP and SoC teams are focusing on “Structural CDC” analysis, which is important but not sufficient. Structural CDC analysis ensures that the d... » read more

← Older posts Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2024 SMG   |  Terms of Service  |  Privacy Policy