Impact Of Cryogenic Temps On The Minimum-Operating Voltage Of 5nm FinFETs-Based SRAM (IIT, UC Berkeley et al)


A new technical paper titled "An Investigation of Minimum Supply Voltage of 5nm SRAM from 300K down to 10K" was published by researchers at Indian Institute of Technology, UC Berkeley and Munich Institute of Robotics and Machine Intelligence. Abstract "In this article, we present a comprehensive study of the impact of cryogenic temperatures on the minimum-operating voltage (Vmin) of 5 nm ... » read more

2025-Product Design Enhancement With Test Structures For Non-Contact Detection Of Yield Detractors


Abstract: Detection and monitoring of the yield loss mechanisms and defects in product chips have been a subject of extensive efforts, resulting in multiple useful Design-for-Manufacturing (DFM) and Design-for-Test (DFT) techniques. Defect inspection techniques extend optical inspection further into sub-10 nm nodes, but many buried defects are formed as a result of multi-layer 3-D interaction... » read more

Metrology Analysis Tool For Photolithography Process Characterization At Advanced Nodes


Continued scaling of integrated circuits to smaller dimensions is still a viable way to increase compute power, achieve higher memory cell density, or reduce power consumption. These days, chip makers are using single-digit nanometer figures or even Angstrom to label their manufacturing technology nodes, which are associated with the size of features patterned during the lithography process. ... » read more

Tiny Dots, Big Impact: The Luminous World of Quantum Dots


In the early ’80s, Alexey Ekimov and Louis E. Brus independently researched semiconductor clusters, leading to the discovery of quantum dots (QDs). QDs are nanoscale semiconductor particles with unique optical and electronic properties. In 1993, Moungi Bawendi improved quantum dot production, making them nearly perfect for various applications. By the late ’90s and early 2000s, quantum d... » read more

Characterization, Modeling, And Model Parameter Extraction Of 5nm FinFETs


A technical paper titled “A Comprehensive RF Characterization and Modeling Methodology for the 5nm Technology Node FinFETs” was published by researchers at IIT Kanpur, MaxLinear Inc., and University of California Berkeley. Abstract: "This paper aims to provide insights into the thermal, analog, and RF attributes, as well as a novel modeling methodology, for the FinFET at the industry stan... » read more

Mechanical Characterization Of Ultra Low-k Dielectric Films


Dielectric materials are of critical importance in the function of microelectronic devices because they electrically isolate conductive components from one another in microcircuits. Capacitance between conductors can limit a circuit’s maximum operating frequency, and the capacitance increases in inverse proportion to the separation distance between the conductors. Therefore, to minimize the s... » read more

FEOL Nanosheet Process Flow & Challenges Requiring Metrology Solutions (IBM Watson)


New technical paper titled "Review of nanosheet metrology opportunities for technology readiness," from researchers at IBM Thomas J. Watson Research Ctr. (United States). Abstract (partial): "More than previous technologies, then, nanosheet technology may be when some offline techniques transition from the lab to the fab, as certain critical measurements need to be monitored in real time. T... » read more

Addressing Library Characterization And Verification Challenges Using ML


At advanced process nodes, Liberty or library (.lib) requirements are more demanding due to design complexities, increased number of corners required for timing signoff, and the need for statistical variation modeling. This results in an increase in size, complexity, and the number of .lib characterizations. Validation and verification of these complex and large .lib files is a challenging task... » read more

Addressing Library Characterization And Verification Challenges Using ML


At advanced process nodes, Liberty or library (.lib) requirements are more demanding due to design complexities, increased number of corners required for timing signoff, and the need for statistical variation modeling. This results in an increase in size, complexity, and the number of .lib characterizations. Validation and verification of these complex and large .lib files is a challenging task... » read more

Design Technology Co-Optimization


Rising complexity is making it increasingly difficult to optimize chips for yield and reliability. David Fried, vice president of computational products at Lam Research, examines the benefits of automated rules to manage the relationship between layout and design requirements on one side, and process flows and rules/checks on the other. Benefits include reduced margin, shortened time to market,... » read more

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