tag: characterization

Metrology Analysis Tool For Photolithography Process Characterization At Advanced Nodes
By Wolfgang Demmerle - 23 Jul, 2024 - Comments: 0

Continued scaling of integrated circuits to smaller dimensions is still a viable way to increase compute power, achieve higher memory cell density, or reduce power consumption. These days, chip makers are using single-digit nanometer figures or even Angstrom to label their manufacturing technology nodes, which are associated with the size of features patterned during the lithography process. ... » read more

Tiny Dots, Big Impact: The Luminous World of Quantum Dots
By Xia Stammer - 07 Nov, 2023 - Comments: 0

In the early ’80s, Alexey Ekimov and Louis E. Brus independently researched semiconductor clusters, leading to the discovery of quantum dots (QDs). QDs are nanoscale semiconductor particles with unique optical and electronic properties. In 1993, Moungi Bawendi improved quantum dot production, making them nearly perfect for various applications. By the late ’90s and early 2000s, quantum d... » read more

Characterization, Modeling, And Model Parameter Extraction Of 5nm FinFETs
By Technical Paper Link - 06 Oct, 2023 - Comments: 0

A technical paper titled “A Comprehensive RF Characterization and Modeling Methodology for the 5nm Technology Node FinFETs” was published by researchers at IIT Kanpur, MaxLinear Inc., and University of California Berkeley. Abstract: "This paper aims to provide insights into the thermal, analog, and RF attributes, as well as a novel modeling methodology, for the FinFET at the industry stan... » read more

Mechanical Characterization Of Ultra Low-k Dielectric Films
By Bruker - 08 Feb, 2023 - Comments: 0

Dielectric materials are of critical importance in the function of microelectronic devices because they electrically isolate conductive components from one another in microcircuits. Capacitance between conductors can limit a circuit’s maximum operating frequency, and the capacitance increases in inverse proportion to the separation distance between the conductors. Therefore, to minimize the s... » read more

FEOL Nanosheet Process Flow & Challenges Requiring Metrology Solutions (IBM Watson)
By Technical Paper Link - 08 Jul, 2022 - Comments: 0

New technical paper titled "Review of nanosheet metrology opportunities for technology readiness," from researchers at IBM Thomas J. Watson Research Ctr. (United States). Abstract (partial): "More than previous technologies, then, nanosheet technology may be when some offline techniques transition from the lab to the fab, as certain critical measurements need to be monitored in real time. T... » read more

Addressing Library Characterization And Verification Challenges Using ML
By Siemens EDA - 23 Feb, 2022 - Comments: 0

At advanced process nodes, Liberty or library (.lib) requirements are more demanding due to design complexities, increased number of corners required for timing signoff, and the need for statistical variation modeling. This results in an increase in size, complexity, and the number of .lib characterizations. Validation and verification of these complex and large .lib files is a challenging task... » read more

Addressing Library Characterization And Verification Challenges Using ML
By Siemens EDA - 02 Feb, 2022 - Comments: 0

At advanced process nodes, Liberty or library (.lib) requirements are more demanding due to design complexities, increased number of corners required for timing signoff, and the need for statistical variation modeling. This results in an increase in size, complexity, and the number of .lib characterizations. Validation and verification of these complex and large .lib files is a challenging task... » read more

Design Technology Co-Optimization
By Ed Sperling - 18 Jan, 2022 - Comments: 0

Rising complexity is making it increasingly difficult to optimize chips for yield and reliability. David Fried, vice president of computational products at Lam Research, examines the benefits of automated rules to manage the relationship between layout and design requirements on one side, and process flows and rules/checks on the other. Benefits include reduced margin, shortened time to market,... » read more

A Deeper Look into RowHammer’s Sensitivities: Experimental Analysis of Real DRAM Chips and Implications on Future Attacks and Defenses
By Technical Paper Link - 14 Nov, 2021 - Comments: 0

Abstract "RowHammer is a circuit-level DRAM vulnerability where repeatedly accessing (i.e., hammering) a DRAM row can cause bit flips in physically nearby rows. The RowHammer vulnerability worsens as DRAM cell size and cell-to-cell spacing shrink. Recent studies demonstrate that modern DRAM chips, including chips previously marketed as RowHammer-safe, are even more vulnerable to RowHammer than... » read more

Model Variation And Its Impact On Cell Characterization
By Umang Doshi - 05 Nov, 2020 - Comments: 0

EDA (Electronic Design Automation) cell characterization tools have been used extensively to generate models for timing, power and noise at a rapidly growing number of process corners. Today, model variation has become a critical component of cell characterization. Variation can impact circuit timing due to process, voltage, and temperature changes and can lead to timing violations, resulting i... » read more

← Older posts

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2024 SMG   |  Terms of Service  |  Privacy Policy