tag: chiplets

Planning EDA’s Next Steps
By Ed Sperling - 24 Mar, 2022 - Comments: 0

Anirudh Devgan, Cadence's new CEO, and the recipient of the Phil Kaufman Award in December, sat down with Semiconductor Engineering to talk about what's next in EDA, the underlying technology and business challenges and changes, and new markets that are unfolding for floor-planning, verification, CFD, and advanced packaging. SE: Where does EDA need to improve? Devgan: We have made it much... » read more

Chiplets Enter The Supercomputer Race
By Mark LaPedus - 17 Mar, 2022 - Comments: 0

Several entities from various nations are racing each other to deliver and deploy chiplet-based exascale supercomputers, a new class of systems that are 1,000x faster than today’s supercomputers. The latest exascale supercomputer CPU and GPU designs mix and match complex dies in advanced packages, adding a new level of flexibility and customization for supercomputers. For years, various na... » read more

Designing a 2048-Chiplet, 14336-Core Waferscale Processor
By Technical Paper Link - 14 Mar, 2022 - Comments: 0

Abstract "Waferscale processor systems can provide the large number of cores, and memory bandwidth required by today’s highly parallel workloads. One approach to building waferscale systems is to use a chiplet-based architecture where pre-tested chiplets are integrated on a passive silicon-interconnect wafer. This technology allows heterogeneous integration and can provide significant perfor... » read more

A Practical Approach To DFT For Large SoCs And AI Architectures, Part II
By Rahul Singhal - 08 Mar, 2022 - Comments: 0

By Rahul Singhal and Giri Podichetty Part I of this article discusses the design-for-test (DFT) challenges of AI designs and strategies to address them at the die level. This part focuses on the test requirements of AI chips that integrate multiple dies and memories on the same package. Why 2.5D/3D chiplet-based designs for AI SoCs? Many semiconductor companies are adopting chiplet-based d... » read more

Which Processor Is Best?
By Ed Sperling - 01 Mar, 2022 - Comments: 2

Intel's embrace of RISC-V represents a landmark shift in the processor world. It's a recognition that no single company can own the data center anymore, upending a revenue model that has persisted since the earliest days of computing. Intel gained traction in that market in the early 1990s with the explosion of commodity servers, but its role is changing as processors become more customized and... » read more

Unintended Coupling Issues Grow
By Brian Bailey - 24 Feb, 2022 - Comments: 0

The number of indirect and often unexpected ways in which one design element may be affected by another is growing, making it more difficult to ensure a chip — or multiple chips in a package — will perform reliably. Long gone are the days when the only way that one part of a circuit could influence another was by an intended wire connecting them. As geometries get smaller, frequencies go... » read more

Transistors Reach Tipping Point At 3nm
By Mark LaPedus - 23 Feb, 2022 - Comments: 1

The semiconductor industry is making its first major change in a new transistor type in more than a decade, moving toward a next-generation structure called gate-all-around (GAA) FETs. Although GAA transistors have yet to ship, many industry experts are wondering how long this technology will deliver — and what new architecture will take over from there. Barring major delays, today’s GAA... » read more

Thermal Management Implications For Heterogeneous Integrated Packaging
By Cameron Nelson - 17 Feb, 2022 - Comments: 1

As the semiconductor industry reaches lower process nodes, silicon designers struggle to have Moore's Law produce the results achieved in earlier generations. Increasing the die size in a monolithic system on chip (SoC) designs is no longer economically viable. The breakdown of monolithic SoCs into specialized chips, referred to as chiplets, presents significant benefits in terms of cost, yield... » read more

Design Challenges Increasing For Mixed-Die Packages
By Ann Mutschler - 09 Feb, 2022 - Comments: 0

The entire semiconductor ecosystem is starting to tackle a long list of technology and business changes that will be needed to continue scaling beyond Moore's Law, making heterogeneous combinations of die easier, cheaper, and more predictable. There are a number of benefits to mixing die and putting them together in a modular way. From a design standpoint, this approach provides access to th... » read more

Next-Gen 3D Chip/Packaging Race Begins
By Mark LaPedus - 31 Jan, 2022 - Comments: 5

The first wave of chips is hitting the market using a technology called hybrid bonding, setting the stage for a new and competitive era of 3D-based chip products and advanced packages. AMD is the first vendor to unveil chips using copper hybrid bonding, an advanced die-stacking technology that enables next-generation 3D-like devices and packages. Hybrid bonding stacks and connects chips usin... » read more

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