Exploring Process Scenarios To Improve DRAM Device Performance

By Yu De Chen - 18 Apr, 2024 - Comments: 0

In the world of advanced semiconductor fabrication, creating precise device profiles (edge shapes) is an important step in achieving targeted on-chip electrical performance. For example, saddle fin profiles in a DRAM memory device must be precisely fabricated during process development in order to avoid memory performance issues. Saddle fins were introduced in DRAM devices to increase channel l... » read more

Review Of Virtual Wafer Process Modeling And Metrology For Advanced Technology Development

By Coventor - 17 Apr, 2024 - Comments: 0

Semiconductor logic and memory technology development continues to push the limits of process complexity and cost, especially as the industry migrates to the 5 nm node and beyond. Optimization of the process flow and ultimately quantifying its physical and electrical properties are critical steps in yielding mature technology. The standard build, test, and wait model of technology development ... » read more

Techniques To Identify And Correct Asymmetric Wafer Map Defects Caused By Design And Process Errors

By James Kim - 22 Feb, 2024 - Comments: 0

Asymmetries in wafer map defects are usually treated as random production hardware defects. For example, asymmetric wafer defects can be caused by particles inadvertently deposited on a wafer during any number of process steps. In this article, I want to share a different mechanism that can cause wafer defects. Namely, that these defects can be structural defects that are caused by a biased dep... » read more

Fan-Out Panel-Level Packaging Hurdles

By Anne Meixner - 24 Jan, 2024 - Comments: 0

Fan-out panel-level packaging (FOPLP) promises to significantly lower assembly costs over fan-out wafer-level packaging, providing the relevant processes for die placement, molding and redistribution layers (RDLs) formation can be scaled up with equivalent yield. There is still much work to be done before that happens. Until now, FOPLP has been adopted for devices that are manufactured in ve... » read more

Navigating Heat In Advanced Packaging

By Gregory Haley - 18 Jan, 2024 - Comments: 0

The integration of multiple heterogeneous dies in a package is pivotal for extending Moore’s Law and enhancing performance, power efficiency, and functionality, but it also is raising significant issues over how to manage the thermal load. Advanced packaging provides a way to pack more features and functions into a device, increasingly by stacking various components vertically rather than ... » read more

Developing ReRAM As Next Generation On-Chip Memory For Machine Learning, Image Processing And Other Advanced CPU Applications

By Brett Lowe - 18 Jan, 2024 - Comments: 0

In modern CPU device operation, 80% to 90% of energy consumption and timing delays are caused by the movement of data between the CPU and off-chip memory. To alleviate this performance concern, designers are adding additional on-chip memory to their CPUs. Traditionally, SRAM has been the most widely used on-chip CPU memory type. Unfortunately, SRAM is currently limited to a size of hundreds of ... » read more

Fabs Begin Ramping Up Machine Learning

By Anne Meixner - 19 Dec, 2023 - Comments: 0

Fabs are beginning to deploy machine learning models to drill deep into complex processes, leveraging both vast compute power and significant advances in ML. All of this is necessary as dimensions shrink and complexity increases with new materials and structures, processes, and packaging options, and as demand for reliability increases. Building robust models requires training the algorithms... » read more

Improving Semiconductor Yield Using Large Area Analysis

By Jacky Huang - 19 Dec, 2023 - Comments: 0

Design rule checking (DRC) is a technique used during chip design to ensure that a device can successfully be manufactured at high yield. Design rules are established based on the limits and variability of equipment and process technologies in use. DRC checking ensures that a design meets manufacturing requirements and will not result in a chip failure or DRC “violation.” Common DRC rules i... » read more

Important Process Parameter And Its Sensitivity Check By Virtual Fabrication: Channel Hole Profile Impact On Advanced 3D NAND Structure

By Coventor - 19 Dec, 2023 - Comments: 0

A virtual DOE-based process sensitivity check was performed for two tiers of channel holes in a 3D NAND device. The channel hole tilt distance, twist angle, and their sensitivities to the visible area in silicon-oxide-nitride-oxide (SONO) punch process were analyzed. The results show that controlling the upper tilt distance is more important for offering a larger visible area. Also, a negative ... » read more

Blog Review: December 13

By Jesse Allen - 13 Dec, 2023 - Comments: 0

Synopsys' Charles Dittmer discusses key and emerging use cases for Bluetooth Low Energy and how combining BLE with other wireless protocols can open new avenues of functionality for application areas including automotive, hearables, and retail. Cadence's Neelabh Singh points out changes in the terminologies describing USB4 links and shows the various possible link configurations put forth by... » read more

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tag: Coventor

Exploring Process Scenarios To Improve DRAM Device Performance

Review Of Virtual Wafer Process Modeling And Metrology For Advanced Technology Development

Techniques To Identify And Correct Asymmetric Wafer Map Defects Caused By Design And Process Errors

Fan-Out Panel-Level Packaging Hurdles

Navigating Heat In Advanced Packaging

Developing ReRAM As Next Generation On-Chip Memory For Machine Learning, Image Processing And Other Advanced CPU Applications

Fabs Begin Ramping Up Machine Learning

Improving Semiconductor Yield Using Large Area Analysis

Important Process Parameter And Its Sensitivity Check By Virtual Fabrication: Channel Hole Profile Impact On Advanced 3D NAND Structure

Blog Review: December 13

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