tag: Coventor

Optimizing DRAM Development Using Directed Self-Assembly (DSA)
By Coventor - 24 Feb, 2017 - Comments: 0

Directed Self-Assembly (DSA) is an emerging technology that has the ability to substantially improve lithographic manufacturing of semiconductor devices. In DSA, copolymer materials self-assemble to form nanoscale resolution patterns on the semiconductor substrate. DSA technologies hold the promise to substantially improve the resolution of existing lithographic processes (such as self-aligned ... » read more

MEMS: A Tale Of Two Tough Markets
By Ed Sperling - 22 Feb, 2017 - Comments: 0

The MEMS market is growing rapidly, profits not so much. In most market segments, this would be a signal that more automation and standardization are required. But in the microelectromechanical systems world, fixes aren't so simple. And even where something can be automated, that automation doesn't work all the time. In fact, while MEMS devices are extremely difficult to design, build and ma... » read more

Semiconductor Process Development: Finding A Faster Way To Profitability
By Katherine Gambino - 20 Feb, 2017 - Comments: 0

Building a chip fabrication facility requires billions of dollars in investment for land, buildings, processing equipment, chemical and hazardous material safety, not to mention the deployment of hundreds of highly experienced process engineering and manufacturing personnel. Bringing up an advanced semiconductor process in any fab, new or established, is a several-hundred-million dollar effort,... » read more

Battling Fab Cycle Times
By Mark LaPedus - 16 Feb, 2017 - Comments: 9

The shift from planar devices to finFETs enables chipmakers to scale their processes and devices from 16nm/14nm and beyond, but the industry faces several challenges at each node. Cost and technical issues are the obvious challenges. In addition, cycle time—a key but less publicized part of the chip-scaling equation—also is increasing at every turn, creating more angst for chipmakers and... » read more

BEOL Issues At 10nm And 7nm
By Ed Sperling - 31 Jan, 2017 - Comments: 0

Semiconductor Engineering sat down to discuss problems with the back end of line at leading-edge nodes with Craig Child, senior manager and deputy director for [getentity id="22819" e_name="GlobalFoundries'"] advanced technology development integration unit; Paul Besser, senior technology director at [getentity id="22820" comment="Lam Research"]; David Fried, CTO at [getentity id="22210" e_name... » read more

New Techniques To Analyze And Reduce Etch Variation
By Coventor - 25 Jan, 2017 - Comments: 1

Time division multiplex (TDM) plasma etch processes (commonly referred to as Deep Reactive ION Etching [“DRIE”]) use alternating deposition and etch steps cyclically to produce high aspect ratio structures on a silicon substrate. These etch processes have been widely applied in the manufacturing of silicon MEMS devices, and more recently in creating through silicon vias in 3D silicon struct... » read more

New Embedded Memories Ahead
By Mark LaPedus - 25 Jan, 2017 - Comments: 0

The embedded memory market is beginning to heat up, fueled by a new wave of microcontrollers (MCUs) and related chips that will likely require new and more capable nonvolatile memory types. The industry is moving on several different fronts in the embedded memory landscape. On one front, traditional solutions are advancing. On another front, several vendors are positioning the next-generatio... » read more

Integrating Process Models With TCAD Simulation…
By Jacky Huang - 23 Jan, 2017 - Comments: 2

Novel semiconductor technologies are creating complex process flows, which are needed to support the manufacturing of advanced 3D semiconductor structures. It can be helpful to model process flows, and their effect on a novel device, prior to physical fabrication. Process modeling is a technique that can predict the 3D structure of a device using an understanding of unit process steps. Durin... » read more

Transferring Skills Getting Harder
By Ed Sperling - 19 Jan, 2017 - Comments: 0

Rising complexity in developing chips at advanced nodes, and an almost perpetual barrage of new engineering challenges at each new node, are making it more difficult for everyone involved to maintain consistent skill levels across a growing number of interrelated technologies. The result is that engineers are being forced to specialize, but when they work with other engineers with different ... » read more

China Unveils Memory Plans
By Mark LaPedus - 19 Jan, 2017 - Comments: 2

Backed by billions of dollars in government funding, China in 2014 launched a major initiative to advance its domestic semiconductor, IC-packaging and other electronic sectors. So far, though, the results are mixed. China is making progress in IC-packaging, but the nation’s efforts to advance its domestic logic and memory sectors are still a work in progress. In fact, China has yet to achi... » read more

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