The Week In Review: Manufacturing

SPIE news; EUV update; lab to fab; SMIC joins eBeam.


SPIE news
At this week’s SPIE Advanced Lithography conference, the industry paid close attention to the progress of extreme ultraviolet (EUV) lithography.

Here’s the general report card: EUV is making noticeable progress, but there are still some challenges ahead, such as the power source, resists and pellicles. Several issues need to be resolved before chipmakers can put EUV into mass production at 7nm and/or 5nm.

At SPIE, ASML provided an update on its latest and previously-disclosed EUV scanner. The system, dubbed the NXE:3400B, is geared for 5nm in logic and less than 15nm for DRAM. Based on a 13.5nm wavelength, the system has a numerical aperture (NA) of 0.33 and a 13nm resolution.

The tool, which will ship soon, will incorporate a more powerful source. Last year, ASML moved from an 80-watt to a 125-watt source, boosting the throughputs from around 60 wafers an hour (wph) to 85 wph.

Now, the EUV source has been boosted to 145 watts. So, the NXE:3400B will initially incorporate ASML’s 145-watt source, which translates to 100 wph. “We are running at about 100 wafers an hour. It’s enough for companies to get started and get it integrated,” said Michael Lercel, director of product marketing at ASML. “The target is still to have it run at 125 wafers an hour.”

In fact, ASML has developed a more powerful source operating at 210 watts, which will enable 125 wph. The company plans to ship the 210-watt source sometime this year.

Meanwhile, the projection optics in the NXE:3400B incorporate a new illuminator, enabling the system to shape the illumination modes. In addition, the system has a 0.3nm CD uniformity for lines and spaces. It demonstrated features down to 13nm line/space.

All told, chipmakers want EUV for good reason. It reduces the masks required and simplifies the production flow at advanced nodes. For example, it takes 1 to 1.5 days to process a mask layer. With multi-patterning at 7nm, it takes close to five months to ship wafers. “With EUV, you replace a bunch of (mask) layers,” Lercel said. “That gets wafers out the door at least a month early.”

Most observers believe ASML’s EUV technology is making significant progress. “EUV development (is) progressing surprisingly well. We heard from several chipmakers this week; all noted that extreme ultraviolet progress has been good and there are no major roadblocks to adoption, although there is still a lot of work to be done to prepare EUV for high-volume manufacturing,” said Weston Twigg, an analyst with Pacific Crest Securities, in a research note.

“Insertion is still planned for the 7nm node at Intel and 7nm or 5nm at Samsung and TSMC,” Twigg said. “With respect to timing of EUV adoption, Intel is still planning on 7nm node insertion, though the company continues to emphasize that it will only adopt the technology if it is ready. Intel’s current 10nm ramp appears to be behind schedule, which could push out the 7nm ramp; applying a three-year cadence would put the 7nm ramp in 2020, while a 3.5-year cadence would put the ramp in 2021.”

Based on data from Intel, Samsung and others, there are still some challenges with EUV:

*“Availability is now over 75% at Intel based on a four-week average. Intel noted that the source is still the main reason for tool downtime, while Samsung highlighted low collector lifetime as a major availability problem,” he said.

*The resists require more development.

*In EUV, there are several issues, such as stochastics, line-edge roughness (LER) and others. This is caused by photon shot noise and other sources.

*Pellicles. ASML is developing a polysilicon-based pellicle for the system. At present, ASML is readying the pellicles for EUV. Still to be seen, however, is if the pellicle can withstand the heat from a 140- or 210-watt source.

*Actinic mask inspection. No one is developing this technology.


Generally, the company that succeeds–and garners the initial profits–is the one that introduces a product or technology first for a given market. Of course, that is not always the case. At times, the fast follower can also reap the rewards with a good or better technology.

In either case, bringing technology from the lab to the fab is becoming more difficult at each node or turn. For one thing, the devices and process technologies are more complex. “The challenges are everywhere,” said David Fried, chief technology officer at Coventor. “This is because we’ve pushed technology much further than anybody predicted that we could.”

Then, there is the time-to-market issue. “Basically, the net is that we see a lot of research papers and publications about new materials, structures and techniques,” Fried said. “Then, we see the manufacturing announcements, teardowns and analysis that include those new materials, devices and structures. But there is like four, five, six or seven years between those research papers and those manufacturing announcements of the teardowns.”

During a keynote at SPIE, Fried addressed several issues, including a major one—How to speed up the R&D cycle. In the keynote, entitled “Technology Development: the ‘In Between,’ ” Fried discussed the risk and complexity of the time “in between” research ideas, new technologies and products in the semiconductor industry.

According to Fried, R&D technologies must look at the problem differently. Here are just a few things that technologists must consider:

Make the big decisions earlier in the R&D cycle. “You can’t make all of your decisions serially in technology development. You can’t make one decision and then figure out what the next decision is and make that one,” he said.

The problem? “You never get to the end of the road. You have to vet out some of your big decisions earlier,” he said. The idea is to make those big branch decisions earlier, he said.

Look at the variations earlier in the cycle. At times, there is a temptation to devise a technology “based on its nominal performance and then try to survive the variation,” he said. Instead, technologists should consider changing their mindset. They should consider thinking “about the variation and the process window, and setting up a technology whose nominal allows you to fit it through that window,” he said.

Vet out the process earlier. The idea is to look at the processes and interactions before they are inserted into the fab. Otherwise, a big and costly problem could occur during the flow.

Those are just some of the considerations for the R&D staff. There are several ways to solve the problem. For example, Coventor recently rolled out SEMulator3D 6.0 – the latest version of its semiconductor virtual fabrication platform. SEMulator3D is a modeling and analysis platform. It enables researchers to develop a “virtual fabrication” of an advanced manufacturing process, allowing engineers to understand manufacturing effects early in the development process and reduce time-consuming and costly silicon learning cycles.


The eBeam Initiative, a forum dedicated to the education and promotion of new semiconductor manufacturing approaches based on electron beam (eBeam) technologies, announced that Semiconductor Manufacturing International Corp. (SMIC) has joined the eBeam Initiative. SMIC is China’s largest foundry vendor. “SMIC is pleased to have been a participant in the eBeam Initiative’s annual mask makers survey since it was commissioned two years ago,” said Eric Guo, senior director of the mask operation at SMIC. “As a new member of the eBeam Initiative, we look forward to continuing to support projects like the survey that provides a benefit not only to us but to the industry as a whole.”

At the eBeam Initiative event at SPIE, Synopsys gave a presentation on inverse lithography technology (ILT). Here are the slides. In addition, D2S presented a paper on mask modeling in the multi-beam era.

Cadence Design Systems has rolled out the Litho Physical Analyzer (LPA) Production Lithography Unified Solution (PLUS). The technology was developed in partnership with ASML. Cadence LPA PLUS enables engineers to detect lithography hotspots during design implementation and physical signoff and automatically fix them in Cadence design platforms. As a result, designers can improve design reliability and yield, while also accelerating time-to-market.

Dream Chip Technologies has announced the industry`s first 22nm FD-SOI silicon for a new ADAS system-on-chip (SoC) for automotive computer vision applications. The SoC was created in cooperation with ARM, Arteris, Cadence, GlobalFoundries and Invecas. This is part of the European Commission’s ENIAC THINGS2DO reference development platform.

Cypress Semiconductor has sold the subsidiary that owns its semiconductor wafer fabrication facility in Bloomington, Minn. to SkyWater Technology Foundry for $30 million. SkyWater will operate the fab as a standalone business that will manufacture wafers for Cypress and for other semiconductor manufacturers.

TowerJazz has announced that it is the high-volume technology manufacturer for Cavendish Kinetics, a supplier of radio-frequency micro-electromechanical systems (RF MEMS). In addition, TowerJazz and the University of California at San Diego (UCSD) have demonstrated a greater than 12-Gbps phased-array chipset for 5G applications. The chipset operates at 28- to 31-GHz, a new communications band planned for release by the FCC. The chipset uses TowerJazz’s SiGe BiCMOS technology.

Lattice Semiconductor’s shareholders have approved a plan under which the company will be acquired by Canyon Bridge, a group based in China.

Test and measurement
National Instruments (NI) has rolled out NI-RFmx 2.2, the latest version of its measurement software for PXI RF test systems. When used with the second-generation PXI Vector Signal Transceiver (VST), engineers can test 4.5G and 5G RF components, such as transceivers and amplifiers using a wide range of carrier aggregation schemes, even as the 5G standard is still being defined.

Keysight and Samsung have entered into a technology collaboration to enable design, deployment and testing of 5G devices to support early operator trials.

Market research
Eleven companies are forecast to have semiconductor capital expenditure budgets greater than $1.0 billion in 2017, and account for 78% of total worldwide semiconductor industry capital spending this year, according to IC Insights.


memister says:

Reducing the mask count without EUV is where the competitive edge lies. EUV as desired may not be here for quite a while.

memister says:

In 2014, ASML specified throughput at 20 mJ/cm2, it looks like that hasn’t changed but resists have been going way higher.

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