tag: D2S

New BEOL/MOL Breakthroughs?
By Mark LaPedus - 15 Jun, 2017 - Comments: 1

Chipmakers are moving ahead with transistor scaling at advanced nodes, but it's becoming more difficult. The industry is struggling to maintain the same timeline for contacts and interconnects, which represent a larger portion of the cost and unwanted resistance in chips at the most advanced nodes. A leading-edge chip consists of three parts—the transistor, contacts and interconnects. The ... » read more

The Race To 10/7nm
By Mark LaPedus - 22 May, 2017 - Comments: 4

Amid the ongoing ramp of 16/14nm processes in the market, the industry is now gearing up for the next nodes. In fact, GlobalFoundries, Intel, Samsung and TSMC are racing each other to ship 10nm and/or 7nm technologies. The current iterations of 10nm and 7nm technologies are scaled versions of today’s 16nm/14nm finFETs with traditional copper interconnects, high-k/metal-gate and low-k diele... » read more

Inside Lithography And Masks
By Mark LaPedus - 01 May, 2017 - Comments: 1

Semiconductor Engineering sat down to discuss lithography and photomask technologies with Gregory McIntyre, director of the Advanced Patterning Department at [getentity id="22217" comment="IMEC"]; Harry Levinson, senior fellow and senior director of technology research at [getentity id="22819" comment="GlobalFoundries"]; David Fried, chief technology officer at [getentity id="22210" e_name="Cov... » read more

The Week In Review: Manufacturing
By Mark LaPedus - 07 Apr, 2017 - Comments: 0

Mask and fab equipment Seeking to speed up the semiconductor design and manufacturing process, D2S has rolled out its fifth-generation computational design platform (CDP). D2S, a supplier of GPU-accelerated computational systems or platforms, said the latest CDP is designed to enable faster simulations for a range of applications. Using Nvidia’s Pascal-based Tesla P40 GPUs, D2S’ fifth-... » read more

Inside Lithography And Masks
By Mark LaPedus - 05 Apr, 2017 - Comments: 3

Semiconductor Engineering sat down to discuss lithography and photomask technologies with Gregory McIntyre, director of the Advanced Patterning Department at [getentity id="22217" e_name="Imec"]; Harry Levinson, senior fellow and senior director of technology research at [getentity id="22819" comment="GlobalFoundries"]; David Fried, chief technology officer at [getentity id="22210" e_name="Cove... » read more

The Week In Review: Manufacturing
By Mark LaPedus - 31 Mar, 2017 - Comments: 0

Chipmakers At an event, Intel’s Technology and Manufacturing group outlined the company's vision. As part of the event, Intel reiterated what many are saying—the current node designations are meaningless and misleading. “For example, Intel estimates that its 14nm solution that has been out in the market since 2014 should be equal to 10nm solutions released by competitors in the near futu... » read more

The Week In Review: Manufacturing
By Mark LaPedus - 24 Mar, 2017 - Comments: 0

Chipmakers China’s IC industry is embarking on a recruitment drive to prepare for the operation of new fabs in 2018, according to TrendForce. “TrendForce’s latest analysis on China’s semiconductor sector reveals that the country’s domestic IC manufacturers are affecting the movement of industry talent worldwide as they continue to aggressively headhunt for senior managers and enginee... » read more

Inside Lithography And Masks
By Mark LaPedus - 16 Mar, 2017 - Comments: 2

Semiconductor Engineering sat down to discuss lithography and photomask technologies with Gregory McIntyre, director of the Advanced Patterning Department at [getentity id="22217" e_name="Imec"]; Harry Levinson, senior fellow and senior director of technology research at [getentity id="22819" comment="GlobalFoundries"]; David Fried, chief technology officer at [getentity id="22210" e_name="Cove... » read more

The Week In Review: Manufacturing
By Mark LaPedus - 03 Mar, 2017 - Comments: 2

SPIE news At this week’s SPIE Advanced Lithography conference, the industry paid close attention to the progress of extreme ultraviolet (EUV) lithography. Here’s the general report card: EUV is making noticeable progress, but there are still some challenges ahead, such as the power source, resists and pellicles. Several issues need to be resolved before chipmakers can put EUV into mass... » read more

Big Changes In Patterning
By Ed Sperling - 22 Feb, 2017 - Comments: 0

Aki Fujimura, CEO of [getentity id="22864" comment="D2S"], sat down with Semiconductor Engineering to discuss patterning issues at 10nm and below, including mask alignment, the need for GPU acceleration, EUV's future impact on the total number of masks, and what the re-introduction of curvilinear shapes will mean for design. SE: Patterning issues are getting a lot of attention at 10nm and 7n... » read more

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