Precise Control Needed For Copper Plating And CMP

By Anne Meixner - 20 Jun, 2024 - Comments: 0

Chipmakers are relying on machine learning for electroplating and wafer cleaning at leading-edge process nodes, augmenting traditional fault detection/classification and statistical process control in order to extend the usefulness of copper interconnects. Copper is well understood and easy to work with, but it is running out of steam. At 5nm and below, copper plating tools are struggling to... » read more

Negative-Tone Photosensitive Polymeric Bonding Material To Enable Room Temperature Prebond For Cu/Polymer Hybrid Bonding

By Brewer Science - 18 Oct, 2023 - Comments: 0

An evaluation of a negative-tone i-line photosensitive polymeric bonding material for achieving prebonding in Cu/polymer hybrid bonding at low temperatures via the Cu damascene process. The polymeric material has a Tg≤100∘C ; Young’s modulus of 99 MPa, the dielectric constant of 2.6, and dissipation factor of 0.0016 at 10 GHz. Shear tests revealed a bond shear strength of over 10 MPa when... » read more

Impacts Of Process Flow, Scaling, And Variability On Interconnect Performance

By Lam Research - 26 Apr, 2023 - Comments: 0

Virtual fabrication is used to evaluate the performance of interconnects (line and via resistance, capacitance, etc.) across pitches compatible with either EUV single exposure or SADP for three different process flows: single damascene, dual damascene, and semi-damascene (subtractive metal etch). The effects of process variation for the three flows are also investigated to determine the relativ... » read more

Imaging Of Overlay And Alignment Markers Under Opaque Layers Using Picosecond Laser Acoustic Measurements

By Onto Innovation - 09 Nov, 2021 - Comments: 0

Optically opaque materials present a series of challenges for alignment and overlay in the semi-damascene process flow or after the processing of the magnetic tunnel junction (MTJ) of a Magnetic Random-Access Memory (MRAM). The overlay and alignment of a lithographically defined pattern on top of the pattern and the underlying layer is fundamental to device operation in all multi-layer patterne... » read more

One Micron Damascene Redistribution for Fan-Out Wafer Level Packaging Using a Photosensitive Dielectric Material

By Veeco - 22 May, 2019 - Comments: 0

Authors: Warren W. Flack, Robert Hsieh, Ha-Ai Nguyen Ultratech, a division of Veeco 3050 Zanker Road, San Jose, CA 95134 USA [email protected] John Slabbekoorn, Samuel Suhard, Andy Miller IMEC Kapeldreef 75 B-3001 Leuven, Belgium [email protected] Akito Hiro, Romain Ridremont JSR MICRO NV Technologielaan 8 B-3001 Leuven, Belgium [email protected] Abstract This... » read more

Can Copper Revolutionize Interconnects Again?

By Katherine Derbyshire - 10 Jun, 2015 - Comments: 2

Electromigration and resistivity present serious obstacles to interconnect scaling, as previously discussed. In a copper damascene process, grain growth is constrained by the narrow trenches into which copper is deposited. As the grain size approaches the mean free path of electrons in copper, electron scattering at sidewalls and grain boundaries increases and resistivity jumps. Meanwhile, incr... » read more

What Will Replace Dual Damascene?

By Mark LaPedus - 24 Jan, 2013 - Comments: 0

By Mark LaPedus In the mid-1990s, IBM announced the world’s first devices using a copper dual damascene process. At the time, the dual damascene manufacturing process was hailed as a major breakthrough. The new copper process enabled IC makers to scale the tiny interconnects in a device, as the previous material, aluminum, faced some major limitations. Dual damascene remains the workhorse... » read more

Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer