tag: DDR

CXL Memory: Detailed Characterization Analysis Using Micro-Benchmarks And Real Applications (UIUC, Intel Labs)
By Technical Paper Link - 30 Mar, 2023 - Comments: 0

A new technical paper titled "Demystifying CXL Memory with Genuine CXL-Ready Systems and Devices" was published by researchers at University of Illinois Urbana-Champaign (UIUC) and Intel Labs. Abstract: "The high demand for memory capacity in modern datacenters has led to multiple lines of innovation in memory expansion and disaggregation. One such effort is Compute eXpress Link (CXL)-based... » read more

Efficiently Process Large RM Datasets In Underlying Memory Pool, Disaggregated Over CXL (KAIST)
By Technical Paper Link - 29 Jan, 2023 - Comments: 0

A technical paper titled "Failure Tolerant Training with Persistent Memory Disaggregation over CXL" was published (preprint) by researchers at KAIST and Panmnesia. "TRAININGCXL can efficiently process large-scale recommendation datasets in the pool of disaggregated memory while making training fault tolerant with low overhead," states the paper. Find the technical paper here. or here (IEE... » read more

Jitter Budgeting For Clock Distribution Networks In High-Speed PHYs And SerDes
By Synopsys - 07 Dec, 2022 - Comments: 0

This paper presents a simple but practically precise estimation of periodic single-tone power supply induced jitter (PSIJ) for MOS clock buffer chains. The estimation is algebraically simple for its analytical closed-form expression requiring only a few circuit simulation results without the pre-knowledge of circuit device SPICE parameters. The expression is well suited to predict period PSIJ, ... » read more

How Memory Design Optimizes System Performance
By John Koon - 21 Sep, 2022 - Comments: 0

Exponential increases in data and demand for improved performance to process that data has spawned a variety of new approaches to processor design and packaging, but it also is driving big changes on the memory side. While the underlying technology still looks very familiar, the real shift is in the way those memories are connected to processing elements and various components within a syste... » read more

DDR Memory Test Challenges From DDR3 to DDR5
By Keysight - 21 Sep, 2022 - Comments: 0

Cloud, networking, enterprise, high-performance computing, big data, and artificial intelligence are propelling the development of double data rate (DDR) memory chip technology. Demand for lower power requirements, higher density for more memory storage, and faster transfer speeds are constant. Servers drive the demand for next-generation DDR. Consumers benefit when existing and legacy generati... » read more

Open-Short Normalization Method For A Quick Defect Identification In Branched Traces With High-Resolution Time-Domain Reflectometry
By Advantest - 07 Sep, 2022 - Comments: 0

Time-domain reflectometry (TDR) that employs electro-optical sampling affords excellent resolution at the femtosecond level and exhibits a comprehensible impulse waveform, thereby allowing quick defect identification in a single trace. However, it remains challenging to identify a defect in a trace of multiple branches; the TDR waveform is complex. Generally, the TDR waveform of a defective uni... » read more

DDR5: How Faster Memory Speeds Shape The Future
By Ben Miller - 27 Jun, 2022 - Comments: 0

Faster data processing requires faster memory. Double data rate synchronous dynamic random-access memory (DDR SDRAM) enables the world’s computers to work with the data in memory. DDR is used everywhere — not just in servers, workstations, and desktops, but it is also embedded in consumer electronics, automobiles, and other system designs. DDR SRAM is used for running applications and d... » read more

DRAM Choices Becoming Central Design Considerations
By Ann Mutschler - 12 May, 2022 - Comments: 0

Chipmakers are paying much closer attention to various DRAM options as they grapple with what goes on-chip or into a package, elevating attached memory to a critical design element that can affect system performance, power, and cost. These are increasingly important issues to sort through with a number of tradeoffs, but the general consensus is that to reach the higher levels of performance ... » read more

Improving Memory Efficiency And Performance
By Bryon Moyer - 28 Mar, 2022 - Comments: 0

This is the second of two parts on CXL vs. OMI. Part one can be found here. Memory pooling and sharing are gaining traction as ways of optimizing existing resources to handle increasing data volumes. Using these approaches, memory can be accessed by a number of different machines or processing elements on an as-needed basis. Two protocols, CXL and OMI, are being leveraged to simplify thes... » read more

Changing Server Architectures In The Data Center
By Bryon Moyer - 11 Nov, 2021 - Comments: 1

Data centers are undergoing a fundamental shift to boost server utilization and improve efficiency, optimizing architectures so available compute resources can be leveraged wherever they are needed. Traditionally, data centers were built with racks of servers, each server providing computing, memory, interconnect, and possibly acceleration resources. But when a server is selected, some of th... » read more

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